Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Logic > Gates and Inverters

onsemi NL17SZ32DBVT1G

Name: NL17SZ32DBVT1G
Brand: onsemi
SKU: NL17SZ32DBVT1G
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: NL17SZ32DBVT1G

Manufacturer:: onsemi

Category:: Gates and Inverters

Package:: SC-74A, SOT-753

Datasheet:: NL17SZ32DBVT1G.pdf

Description:: IC GATE OR 1CH 2-INP SC74A

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:2,121

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

NL17SZ32DBVT1G from onsemi is a single 2-input OR gate logic IC designed for low-voltage, high-speed digital signal routing in space-constrained applications. It operates from 1.65 V to 5.5 V, delivers 2.4 ns typical propagation delay at 5 V, supports 24 mA I_O drive at 3.0 V, and features overvoltage-tolerant inputs/outputs up to 5.5 V. It is used in power management sequencing, level translation, and enable-signal combining in portable and industrial control systems.

For engineers reviewing the NL17SZ32DBVT1G datasheet, pinout, applications, or equivalent options, key selection criteria include supply voltage range compatibility, output drive strength at target V_CC, input overvoltage tolerance, IOFF partial power-down capability, and SC-74A package footprint constraints.

Technical Context

The NL17SZ32DBVT1G implements standard positive-logic OR functionality (Y = A + B) using CMOS technology with sub-100-FET complexity. Its input structure supports operation across 1.65–5.5 V while maintaining defined VIH/VIL thresholds per V_CC tier, and its output stage provides rail-to-rail switching with symmetrical sourcing/sinking capability.

IOFF circuitry disables current flow between inputs and outputs when V_CC = 0 V, enabling safe back-driving during partial power-down states. The device exhibits consistent AC timing across −55 °C to +125 °C, with propagation delays ranging from 2.2 ns (5 V, CL = 15 pF) to 12.7 ns (1.65–1.95 V, CL = 15 pF).

Key Specifications

Parameter	Value and Actual Design Meaning
V_CC Range	1.65 V to 5.5 V - Enables direct interface with 1.8 V, 2.5 V, 3.3 V, and 5 V logic domains without level shifters.
t_PD (typ)	2.4 ns at V_CC = 5 V, CL = 15 pF - Supports >200 MHz toggle rates in short-path combinational logic.
I_O Drive	±24 mA at V_CC = 3.0 V - Sufficient to drive multiple 74LVC inputs or small capacitive loads without buffering.
Input Tolerance	Up to 5.5 V independent of V_CC - Allows mixed-supply system interfacing (e.g., 5 V sensor input into 3.3 V MCU domain).
IOFF Support	Active when V_CC = 0 V - Prevents current leakage and bus contention during hot-swap or standby modes.
Operating Temp	−55 °C to +125 °C - Qualified for extended industrial and automotive under-hood environments.
Package	SC-74A (Case 318BQ), 5-pin, 3.0 mm × 1.5 mm - Compatible with high-density PCB layouts and reflow assembly.

Pinout & Package

SC-74A package (Case 318BQ): 5-pin, surface-mount, 3.0 mm × 1.5 mm × 0.95 mm body, 0.95 mm pitch, Pb-free, RoHS compliant.

Pin/Terminal	Circuit Role	Design Meaning
1 (A)	Input A	First OR operand; accepts DC input voltages from 0 V to 5.5 V regardless of V_CC.
2 (B)	Input B	Second OR operand; electrically identical to Pin 1 with same overvoltage tolerance.
3 (GND)	Ground Reference	Return path for all internal logic and output currents; must be low-impedance for noise immunity.
4 (Y)	Output Y	OR result (Y = A + B); rail-to-rail CMOS output capable of sourcing/sinking 24 mA at 3.0 V.
5 (V_CC)	Positive Supply	Primary power rail; enables IOFF protection when held at 0 V during system power sequencing.

Key Features

Feature	Design Value
Wide V_CC range	1.65–5.5 V operation eliminates need for separate voltage translators in multi-rail systems.
Overvoltage-tolerant I/O	Inputs and outputs withstand 5.5 V even when V_CC = 1.65 V, simplifying inter-domain signal routing.
IOFF partial power-down	Blocks current flow between pins when V_CC = 0 V, preventing back-powering and bus conflicts.
Low dynamic power	CPD = 9–11 pF enables <1 mW dynamic power at 10 MHz and 3.3 V, critical for battery-powered devices.
AEC-Q100 qualified option	NL17SZ32DBVT1G is not automotive-qualified; the −Q suffix variant (e.g., NL17SZ32DBVT1G-Q) meets AEC-Q100 Grade 1.

Applications

Power Sequencing Control	Level Translation Interface
Use Scenario: Enabling multiple DC-DC converters in strict start-up order using OR-combined enable signals from supervisor ICs. IC Role / Device Role: Single-gate OR combiner that merges two independent enable sources into one unified enable line. Use Value: Eliminates discrete diode-OR networks, reduces board area by >70%, and ensures clean, glitch-free enable assertion.	Use Scenario: Interfacing a 5 V sensor output to a 3.3 V microcontroller GPIO configured as an interrupt input. IC Role / Device Role: Voltage-tolerant logic buffer that passes high/low states without level-shifting components. Use Value: Maintains signal integrity across supply domains while avoiding added propagation delay from active translators.
Hot-Swap Bus Arbitration	System Reset Coordination
Use Scenario: Detecting insertion of modular daughterboards and asserting a "board present" flag to host controller. IC Role / Device Role: OR gate combining presence-detection signals from multiple slots into a shared status bus. Use Value: IOFF protection prevents back-current from powered slots into unpowered backplane sections during live insertion.	Use Scenario: Combining watchdog timeout, manual reset, and power-on reset signals into a single system-wide reset line. IC Role / Device Role: Active-high OR function ensuring any asserted reset source forces system reset. Use Value: Guarantees deterministic reset behavior with no race conditions or metastability from asynchronous inputs.

Power Sequencing Control

Level Translation Interface

Use Scenario: Enabling multiple DC-DC converters in strict start-up order using OR-combined enable signals from supervisor ICs.

IC Role / Device Role: Single-gate OR combiner that merges two independent enable sources into one unified enable line.

Use Value: Eliminates discrete diode-OR networks, reduces board area by >70%, and ensures clean, glitch-free enable assertion.

Use Scenario: Interfacing a 5 V sensor output to a 3.3 V microcontroller GPIO configured as an interrupt input.

IC Role / Device Role: Voltage-tolerant logic buffer that passes high/low states without level-shifting components.

Use Value: Maintains signal integrity across supply domains while avoiding added propagation delay from active translators.

Hot-Swap Bus Arbitration

System Reset Coordination

Use Scenario: Detecting insertion of modular daughterboards and asserting a "board present" flag to host controller.

IC Role / Device Role: OR gate combining presence-detection signals from multiple slots into a shared status bus.

Use Value: IOFF protection prevents back-current from powered slots into unpowered backplane sections during live insertion.

Use Scenario: Combining watchdog timeout, manual reset, and power-on reset signals into a single system-wide reset line.

IC Role / Device Role: Active-high OR function ensuring any asserted reset source forces system reset.

Use Value: Guarantees deterministic reset behavior with no race conditions or metastability from asynchronous inputs.

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input OR gate applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LVC1G32DBVR	Same SC-74A package; 1.65–5.5 V V_CC; t_PD = 3.7 ns (5 V); IOFF not supported.	Lacks IOFF, limiting use in partial power-down systems; otherwise pin-compatible and functionally identical.	Select when IOFF is unnecessary and TI's qualification ecosystem is preferred.
74AUP1G32GW,125	SC-70-5 package (same pin count, different footprint); 0.8–3.6 V V_CC; t_PD = 6.2 ns (3.3 V); lower I_O (4 mA).	Not drop-in due to SC-70-5 vs. SC-74A mechanical mismatch; suited for ultra-low-power, sub-3.6 V designs only.	Choose for battery-operated devices requiring <1 µA ICC and operating ≤3.6 V.

Compared with SN74LVC1G32DBVR and 74AUP1G32GW,125, the NL17SZ32DBVT1G uniquely combines 2.4 ns speed at 5 V, 24 mA drive, 5.5 V overvoltage tolerance, and IOFF in the SC-74A footprint-making it optimal for robust, mixed-voltage industrial control nodes.

Availability

NL17SZ32DBVT1G is available at Aetrix Electronics and suitable for power sequencing control, level translation interfaces, hot-swap bus arbitration, system reset coordination, and industrial sensor signal conditioning requiring stable component supply and long-term lifecycle support.

Supply support for NL17SZ32DBVT1G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

onsemi (Semiconductor Components Industries, LLC) is a global semiconductor supplier delivering energy-efficient, intelligent power and sensing solutions for automotive, industrial, cloud, medical, and IoT applications.

The NL17SZ32DBVT1G belongs to onsemi's NanoLogic™ family of ultra-small-footprint, high-speed logic ICs engineered for minimal board space and maximum signal integrity in portable, industrial, and communications equipment.

FAQ

What is the maximum operating temperature range for NL17SZ32DBVT1G?

The NL17SZ32DBVT1G is rated for continuous operation from −55 °C to +125 °C ambient temperature. This full industrial temperature range is verified per the Recommended Operating Conditions table in the official datasheet and supports deployment in harsh environments such as motor control enclosures and outdoor infrastructure equipment where thermal cycling is severe.

Does NL17SZ32DBVT1G support partial power-down via IOFF?

Yes, NL17SZ32DBVT1G includes IOFF circuitry that actively disables input and output paths when V_CC = 0 V. This prevents current backflow and bus contention during partial system shutdown, a feature confirmed in the datasheet Features list and DC Electrical Characteristics section under IOFF Power Off Leakage Current specification.

Is NL17SZ32DBVT1G pin-compatible with other SC-74A logic gates?

No-NL17SZ32DBVT1G has a fixed pinout (A-B-GND-Y-V_CC) specific to its OR function and is not pin-compatible with other SC-74A logic gates like inverters or NANDs, which assign different functions to each pin. Always verify pin assignment against Figure 2 and PIN ASSIGNMENT tables in the NL17SZ32 datasheet before layout reuse.

What is the typical propagation delay of NL17SZ32DBVT1G at 3.3 V?

At V_CC = 3.3 V with RL = 1 MΩ and CL = 15 pF, the typical propagation delay (t_PLH/t_PHL) of NL17SZ32DBVT1G is 2.6 ns, as specified in the AC Electrical Characteristics table. This value is measured under standard test conditions and reflects real-world performance in low-capacitance signal routing paths.

Can NL17SZ32DBVT1G safely interface a 5 V signal to a 1.8 V microcontroller input?

Yes-NL17SZ32DBVT1G inputs tolerate up to 5.5 V regardless of V_CC. When powered at 1.8 V, it correctly interprets 5 V as a logic HIGH (VIH ≥ 0.65 × 1.8 V = 1.17 V), and its output swings rail-to-rail, producing a clean 0 V / 1.8 V signal compatible with 1.8 V logic inputs without external resistors or clamps.

NL17SZ32DBVT1G Specifications

Product attributes: Attribute value

Manufacturer:: onsemi

Series:: 17SZ

Package/Case:: SC-74A, SOT-753

Packaging:: Tape & Reel (TR)

Product Status:: Active

Logic Type:: OR Gate

Number of Circuits:: 1

Number of Inputs:: 2

Features:: -

Voltage - Supply:: 1.65V ~ 5.5V

Current - Quiescent (Max):: 1 µA

Current - Output High, Low:: 32mA, 32mA

Input Logic Level - Low:: -

Input Logic Level - High:: -

Max Propagation Delay @ V, Max CL:: 4.5ns @ 5V, 50pF

Operating Temperature:: -55°C ~ 125°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: SC-74A

NL17SZ32DBVT1G FAQ

1.How can I place an order for NL17SZ32DBVT1G through Aetrix?

Please submit a Request for Quotation (RFQ) for NL17SZ32DBVT1G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for NL17SZ32DBVT1G reliable?

The price and inventory of NL17SZ32DBVT1G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NL17SZ32DBVT1G is usually 5 days.

3.What payment methods are accepted for NL17SZ32DBVT1G?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NL17SZ32DBVT1G transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for NL17SZ32DBVT1G?

NL17SZ32DBVT1G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your NL17SZ32DBVT1G order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for NL17SZ32DBVT1G?

For technical support, including NL17SZ32DBVT1G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NL17SZ32DBVT1G requirements.

6.How does Aetrix verify that NL17SZ32DBVT1G is sourced from the original manufacturer or authorized distributors?

All NL17SZ32DBVT1G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NL17SZ32DBVT1G meets industry standards.

7.What is the process for return or replacement of NL17SZ32DBVT1G?

All NL17SZ32DBVT1G units undergo pre-shipment inspection (PSI). If there is an issue with NL17SZ32DBVT1G, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The NL17SZ32DBVT1G part is unused and in its original packaging.

Return procedure for NL17SZ32DBVT1G:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…