onsemi NL37WZ07US
- Part No.:
- NL37WZ07US
- Manufacturer:
- onsemi
- Package:
- 8-VFSOP (0.091", 2.30mm Width)
- Datasheet:
-
NL37WZ07US.pdf
- Description:
- IC BUFF/DVR TRPL N-INV OD US8
- Quantity:
- Payment:

- Shipping:

Inventory:216,000
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Product details
Overview
NL37WZ07US from onsemi is a triple non-inverting buffer IC with open-drain outputs, designed for level-translating logic interfacing in mixed-voltage systems. It operates from 1.65 V to 5.5 V, delivers 2.1 ns typical propagation delay at 5 V, supports ±24 mA output drive at 3.0 V, and features IOFF partial power-down protection - used in automotive body control modules for I²C bus pull-up isolation and sensor interface conditioning.
For engineers reviewing the NL37WZ07US datasheet, pinout, applications, or equivalent options, key selection criteria include open-drain compatibility with 5.5 V-tolerant inputs, AEC-Q100 qualification for automotive use, thermal resistance (250 °C/W), and US8 package footprint constraints in space-constrained ECUs.
Technical Context
The NL37WZ07US implements three independent non-inverting buffers, each with an open-drain output stage enabling wired-AND logic and bidirectional voltage translation. Its IOFF circuitry disables input/output leakage when VCC = 0 V, preventing back-powering of powered-down rails - critical in hot-swap and partial-power-down architectures.
All inputs tolerate up to 5.5 V regardless of VCC level (1.65–5.5 V), and output low-level voltage remains ≤0.42 V at 24 mA sink current (VCC = 3.0 V), ensuring reliable logic-low assertion across supply domains in CAN/LIN transceiver interface circuits and EEPROM reset lines.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.65 V to 5.5 V - enables single-supply operation across 1.8 V, 2.5 V, 3.3 V, and 5 V logic domains |
| tPD (Typ) | 2.1 ns at VCC = 5 V - supports >200 MHz signal routing in timing-critical sensor data paths |
| IOL Max | ±24 mA at VCC = 3.0 V - drives standard 4.7 kΩ pull-up resistors on I²C buses without voltage droop |
| Input Tolerance | Up to 5.5 V - allows direct connection to 5 V microcontrollers while powered from 3.3 V rail |
| IOFF Leakage | ≤10 µA at VCC = 0 V - prevents unintended current flow during system sleep modes |
| Package | US8 (Case 493) - 2.1 mm × 2.0 mm, 0.5 mm pitch surface-mount package for high-density PCB layouts |
| Thermal Resistance | 250 °C/W (JA) - limits junction temperature rise under continuous 24 mA load in still air |
| AEC-Q100 | Qualified - meets Grade 1 (−40 °C to +125 °C) requirements for automotive powertrain and chassis applications |
Pinout & Package
The NL37WZ07US is housed in an 8-pin US8 (Case 493) package - a miniature leadless plastic package with exposed pad, 2.1 mm × 2.0 mm body size, and 0.5 mm lead pitch. Pin 1 is marked by a dot or beveled corner per marking diagram L7/Q4 orientation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (A1) | Input 1 | Non-inverting logic input for first buffer; 5.5 V tolerant, referenced to local VCC |
| 2 (Y3) | Output 3 | Open-drain output of third buffer; requires external pull-up; sinks up to 24 mA |
| 3 (A2) | Input 2 | Non-inverting logic input for second buffer; identical electrical specs to A1 |
| 4 (GND) | Ground | Primary reference for all inputs, outputs, and internal logic; must be low-impedance path |
| 5 (Y2) | Output 2 | Open-drain output of second buffer; electrically isolated from Y1/Y3 except via shared GND |
| 6 (A3) | Input 3 | Non-inverting logic input for third buffer; fully decoupled from A1/A2 in layout |
| 7 (Y1) | Output 1 | Open-drain output of first buffer; supports wired-AND with other open-drain devices |
| 8 (VCC) | Supply | Single positive supply input; powers all three buffers and IOFF circuitry |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range (1.65–5.5 V) | Eliminates need for level shifters when interfacing 1.8 V FPGAs with 5 V peripherals |
| 5.5 V input overvoltage tolerance | Permits direct connection to legacy 5 V GPIOs without external clamping diodes |
| IOFF partial power-down | Blocks >99% of leakage current when VCC is removed - essential for battery-backed subsystems |
| 24 mA sink capability at 3.0 V | Drives standard 4.7 kΩ pull-ups on 3.3 V I²C buses while maintaining VOL < 0.4 V |
| AEC-Q100 Grade 1 qualification | Validated for continuous operation from −40 °C to +125 °C ambient in engine bay modules |
Applications
| Automotive Body Control Unit (BCU) | I²C Bus Level Translation |
|---|---|
Use Scenario: Isolating microcontroller I/O pins from 5 V sensor clusters while operating from a 3.3 V domain. IC Role / Device Role / Timing Role: Triple open-drain buffer providing voltage-domain separation and noise-immune signal routing. Use Value: Enables direct 5 V sensor communication without external level shifters; IOFF prevents backfeed during MCU sleep. | Use Scenario: Interfacing 1.8 V SoC I²C master with 3.3 V EEPROM and 5 V real-time clock. IC Role / Device Role / Timing Role: Open-drain buffer array acting as bidirectional voltage translator on SDA/SCL lines. Use Value: Maintains I²C timing compliance (tPD < 4.8 ns max) while supporting mixed-supply pull-up configurations. |
| Industrial PLC Digital Input Module | Hot-Swappable Peripheral Interface |
Use Scenario: Conditioning 24 V field signals down to 3.3 V logic levels using optocoupler outputs. IC Role / Device Role / Timing Role: Signal conditioner buffering opto-isolator outputs before FPGA capture. Use Value: 5.5 V-tolerant inputs accept opto-output swing directly; 2.1 ns tPD preserves edge integrity for 100 kHz sampling. | Use Scenario: Enabling safe insertion/removal of add-on boards in powered-backplane systems. IC Role / Device Role / Timing Role: Isolation buffer between host controller and peripheral card I/O lines. Use Value: IOFF blocks current flow during card insertion, preventing bus contention and supply rail collapse. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar triple open-drain buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC3G07DCUR | 3.3 V only VCC range (1.65–5.5 V not supported); no AEC-Q100 qualification | Not suitable for automotive Grade 1 environments; lacks IOFF protection | Select only for commercial-grade 3.3 V systems where cost is prioritized over robustness |
| 74LVC3G07GM,132 | Same VCC range and open-drain topology; 2.5 ns tPD at 3.3 V; no automotive qualification | Lacks PPAP documentation and AEC-Q100 test reports required for Tier 1 automotive sourcing | Acceptable for industrial control where extended temperature validation is handled externally |
Compared with SN74LVC3G07DCUR and 74LVC3G07GM,132, the NL37WZ07US uniquely combines AEC-Q100 Grade 1 qualification, IOFF-enabled partial power-down, and guaranteed 5.5 V input tolerance across its full 1.65–5.5 V supply range - making it the only option qualified for safety-critical automotive ECU interfaces requiring zero-risk back-powering prevention.
Availability
NL37WZ07US is available at Aetrix Electronics and suitable for automotive body control units, industrial PLC digital input modules, and hot-swappable peripheral interfaces requiring stable component supply, long-term lifecycle support, and AEC-Q100-compliant sourcing.
Supply support for NL37WZ07US includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (Semiconductor Components Industries, LLC) is a global semiconductor supplier delivering energy-efficient, intelligent power and sensing solutions for automotive, industrial, cloud, medical, and IoT applications.
The NL37WZ07US belongs to onsemi's WZ logic family - ultra-high-speed, low-voltage CMOS buffers engineered specifically for automotive and industrial systems demanding robust voltage translation, low propagation delay, and fail-safe power-down behavior.
FAQ
What is the maximum input voltage the NL37WZ07US can tolerate?
The NL37WZ07US supports DC input voltages up to 5.5 V regardless of VCC level - verified across the full 1.65 V to 5.5 V supply range. This overvoltage tolerance allows direct connection to 5 V logic sources even when the device is powered from 1.8 V or 2.5 V, eliminating external clamping components in mixed-voltage designs. The NL37WZ07US maintains this rating under all operating temperatures (−55 °C to +125 °C).
Does the NL37WZ07US support partial power-down functionality?
Yes, the NL37WZ07US includes IOFF circuitry that actively disables input and output leakage paths when VCC = 0 V. Measured IOFF leakage is ≤10 µA at 5.5 V applied to any input or output terminal, preventing back-powering of inactive supply rails. This feature is validated per AEC-Q100 stress tests and is critical for automotive modules entering low-power sleep states while retaining sensor wake-up capability.
What is the typical propagation delay of the NL37WZ07US at 3.3 V supply?
At VCC = 3.3 V and TA = 25 °C, the NL37WZ07US exhibits a typical propagation delay (tPD) of 2.7 ns for both A-to-Y transitions (tPZL and tPLZ). This value is confirmed in the AC Electrical Characteristics table and applies across the full industrial temperature range (−55 °C to +125 °C), with worst-case delay capped at 6.0 ns - enabling reliable timing in 100+ MHz digital control loops.
Is the NL37WZ07US pin-compatible with other triple buffer devices?
No documented pin-compatible alternatives exist for the NL37WZ07US in the US8 package. While SN74LVC3G07DCUR and 74LVC3G07GM,132 share identical pin numbering (A1/Y3/A2/GND/Y2/A3/Y1/VCC), they lack IOFF and AEC-Q100 qualification - meaning functional substitution requires revalidation of power-down behavior and automotive qualification. The NL37WZ07US pinout is fixed per Figure 2 and cannot be assumed compatible without explicit manufacturer confirmation.
What package type and dimensions does the NL37WZ07US use?
The NL37WZ07US uses the US8 package (Case 493), a leadless 8-pin surface-mount package measuring 2.1 mm × 2.0 mm with 0.5 mm lead pitch. It features an exposed thermal pad and conforms to JEDEC MO-220 standards. The marking code "L7" with "Q4" pin-1 orientation is laser-etched on the top surface, and the device is Pb-free, halogen-free, and RoHS compliant per onsemi's BRD8011/D tape-and-reel specification.
NL37WZ07US Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 37WZ
- Package/Case:
- 8-VFSOP (0.091", 2.30mm Width)
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 3
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- Open Drain
- Current - Output High, Low:
- -, 32mA
- Voltage - Supply:
- 1.65V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- US8
NL37WZ07US FAQ
1.How can I place an order for NL37WZ07US through Aetrix?
Please submit a Request for Quotation (RFQ) for NL37WZ07US on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NL37WZ07US reliable?
The price and inventory of NL37WZ07US are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NL37WZ07US is usually 5 days.
3.What payment methods are accepted for NL37WZ07US?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NL37WZ07US transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NL37WZ07US?
NL37WZ07US orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NL37WZ07US order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NL37WZ07US?
For technical support, including NL37WZ07US datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NL37WZ07US requirements.
6.How does Aetrix verify that NL37WZ07US is sourced from the original manufacturer or authorized distributors?
All NL37WZ07US products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NL37WZ07US meets industry standards.
7.What is the process for return or replacement of NL37WZ07US?
All NL37WZ07US units undergo pre-shipment inspection (PSI). If there is an issue with NL37WZ07US, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NL37WZ07US part is unused and in its original packaging.
Return procedure for NL37WZ07US:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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