onsemi NL37WZ17USG
- Part No.:
- NL37WZ17USG
- Manufacturer:
- onsemi
- Package:
- 8-VFSOP (0.091", 2.30mm Width)
- Datasheet:
-
NL37WZ17USG.pdf
- Description:
- IC BUFFER NON-INVERT 5.5V US8
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
NL37WZ17USG from onsemi is a triple noninverting Schmitt-trigger buffer IC operating from 1.65 V to 5.5 V, delivering 3.2 ns typical propagation delay at 5 V, ±24 mA drive capability at 3.0 V, and overvoltage-tolerant inputs/outputs up to 5.5 V - used in noise-immune signal conditioning for automotive sensor interfaces and industrial control logic.
For engineers reviewing the NL37WZ17USG datasheet, pinout, applications, or equivalent options, key selection criteria include Schmitt-trigger hysteresis (0.7 V typ. at 5.5 V), IOFF partial power-down support, AEC-Q100 qualification, US8 package footprint, and tri-state-compatible output behavior under supply loss.
Technical Context
The NL37WZ17USG implements three independent noninverting buffers, each with Schmitt-trigger input thresholds (VT+ = 3.6 V, VT− = 1.9 V at VCC = 5.5 V) and 0.7 V typical hysteresis, enabling robust noise rejection in slow-rising or noisy digital signals. It supports IOFF circuitry that disables I/O leakage when VCC = 0 V, critical for hot-swap and partial-power-down systems.
Its AC performance is specified across voltage rails (1.65–5.5 V) and temperature (−55 °C to +125 °C), with propagation delays ranging from 2.7 ns (5 V, CL = 15 pF) to 9.2 ns (1.85 V, CL = 15 pF). Input and output capacitance is 2.5 pF each, minimizing loading on driving and driven stages.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.65 V to 5.5 V - enables single-supply operation across 1.8 V, 2.5 V, 3.3 V, and 5 V logic domains. |
| tPD (Typ) | 3.2 ns at VCC = 5 V, CL = 15 pF - ensures fast signal buffering without timing bottlenecks in high-speed control paths. |
| IOH/IOL | ±24 mA at VCC = 3.0 V - drives multiple standard CMOS loads or small LED indicators directly. |
| Input Hysteresis | 0.7 V typical at VCC = 5.5 V - rejects >700 mV of noise on slow or ringing inputs, eliminating false triggering. |
| IOFF Leakage | ≤10 µA at VCC = 0 V - prevents back-driving and bus contention during power sequencing or sleep states. |
| ESD Rating | HBM 2000 V, CDM 1000 V - meets automotive-grade robustness requirements without external protection. |
| Operating Temp | −55 °C to +125 °C - qualified for under-hood automotive and extended-temperature industrial environments. |
Pinout & Package
Package: US8 (Case 493), 8-pin ultra-small surface-mount package (2.1 mm × 2.0 mm × 0.55 mm), lead-free and RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (A1) | Input 1 | Schmitt-trigger input for first buffer channel; accepts 0–5.5 V regardless of VCC level. |
| 2 (Y3) | Output 3 | Noninverting buffered output for third channel; supports tri-state behavior only when enabled externally. |
| 3 (A2) | Input 2 | Schmitt-trigger input for second buffer; electrically isolated from other inputs but shares same VCC/GND. |
| 4 (GND) | Ground | Reference return path for all internal logic and I/O; must be low-impedance for noise immunity. |
| 5 (Y2) | Output 2 | Noninverting buffered output for second channel; capable of sourcing/sinking ±24 mA at 3.0 V. |
| 6 (A3) | Input 3 | Schmitt-trigger input for third buffer; tolerant to overvoltage up to 5.5 V even if VCC is 1.65 V. |
| 7 (Y1) | Output 1 | Noninverting buffered output for first channel; matches propagation delay and drive strength of Y2/Y3. |
| 8 (VCC) | Supply | Positive supply rail; powers all three buffers and enables IOFF functionality when pulled to 0 V. |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger inputs | Provides 0.7 V typical hysteresis at 5.5 V, enabling reliable switching on slow or noisy analog-like signals (e.g., mechanical switch bounce, thermistor outputs). |
| IOFF partial power-down | Disables I/O leakage (<10 µA) when VCC = 0 V, preventing current backflow into powered subsystems during hot-plug or power-gating sequences. |
| Overvoltage-tolerant I/O | Accepts inputs and drives outputs up to 5.5 V independently of VCC (1.65–5.5 V), simplifying level-shifting between mixed-voltage domains. |
| AEC-Q100 qualified | Qualified to Grade 1 (−40 °C to +125 °C ambient) per Rev. G, with PPAP documentation available - suitable for automotive body electronics and ADAS sensor preprocessing. |
| Low dynamic power | CPD = 11 pF at 5.5 V enables <1.5 mW active power at 10 MHz (no load), reducing thermal load in dense PCB layouts. |
Applications
| Automotive Door Module Signal Conditioning | Industrial PLC Input Debouncing |
|---|---|
Use Scenario: Buffering and cleaning signals from mechanical door latch switches exposed to EMI and contact bounce in vehicle door modules. IC Role / Device Role / Timing Role: Triple Schmitt-trigger buffer providing noise-immune digital conditioning for three independent switch inputs before MCU sampling. Use Value: Eliminates need for external RC filters or firmware debouncing; hysteresis rejects >700 mV noise spikes while maintaining <3.2 ns signal delay. | Use Scenario: Interfacing 24 V industrial limit switches to 3.3 V PLC input cards through resistive dividers and signal conditioning. IC Role / Device Role / Timing Role: Level-tolerant buffer isolating legacy 24 V field signals from low-voltage logic, with overvoltage-safe inputs up to 5.5 V. Use Value: Enables direct connection after simple resistor divider without clamping diodes; IOFF prevents backfeed during controller power cycling. |
| Medical Infusion Pump Sensor Interface | Smart Energy Meter Tamper Detection |
Use Scenario: Conditioning pulse outputs from flow sensors subject to cable-induced ringing and ESD transients in battery-powered infusion pumps. IC Role / Device Role / Timing Role: High-immunity buffer stage before microcontroller capture timer, ensuring clean edge detection despite long trace lengths. Use Value: 2000 V HBM ESD rating and 0.7 V hysteresis suppress transient-induced false counts; operates down to 1.65 V for extended battery life. | Use Scenario: Detecting physical tampering via microswitches mounted on meter enclosures, where contacts suffer oxidation and slow rise times. IC Role / Device Role / Timing Role: Schmitt-trigger front-end converting marginal switch transitions into clean logic-level pulses for secure microcontroller monitoring. Use Value: Rejects millisecond-scale contact chatter without software overhead; −55 °C to +125 °C rating ensures reliability in outdoor meter installations. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Schmitt-trigger buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G17DBVR | Single-channel, lower drive (±24 mA at 3.3 V), no IOFF, same US8 package. | Lacks partial power-down protection and AEC-Q100 qualification; suitable for commercial-only designs. | Select when only one buffer is needed and automotive qualification is unnecessary. |
| MC74VHC1GT50DTT1G | Single noninverting buffer (no Schmitt), 3.3 V optimized, no overvoltage tolerance beyond VCC. | No hysteresis or noise immunity; requires clean input signals and external protection for 5.5 V inputs. | Choose only for noise-free, single-rail 3.3 V systems where Schmitt functionality is not required. |
Compared with SN74LVC1G17DBVR and MC74VHC1GT50DTT1G, the NL37WZ17USG uniquely delivers triple-channel Schmitt buffering with IOFF, AEC-Q100 qualification, and 5.5 V overvoltage tolerance - making it the only option among the three qualified for automotive hot-swap sensor interfaces requiring simultaneous noise rejection and power sequencing safety.
Availability
NL37WZ17USG is available at Aetrix Electronics and suitable for automotive body electronics, industrial PLC input conditioning, and medical device sensor interfacing requiring stable component supply, long-term lifecycle support, and AEC-Q100 compliance.
Supply support for NL37WZ17USG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (Semiconductor Components Industries, LLC) is a global semiconductor supplier focused on energy-efficient technologies for automotive, industrial, cloud, and IoT applications.
The NL37WZ17USG belongs to onsemi's TinyLogic® WZ high-speed logic family, designed specifically for space-constrained, low-power, noise-immune digital signal conditioning in harsh environments.
FAQ
What is the maximum input voltage the NL37WZ17USG can tolerate when VCC = 1.65 V?
The NL37WZ17USG supports input voltages up to 5.5 V regardless of VCC level, including when VCC = 1.65 V. This overvoltage tolerance allows safe interfacing with higher-voltage signals without external level-shifting components, as confirmed in the Absolute Maximum Ratings table (VIN = −0.5 V to +6.5 V) and Recommended Operating Conditions (VIN = 0 to 5.5 V).
Does the NL37WZ17USG support true tri-state outputs?
No, the NL37WZ17USG does not have an enable pin or internal tri-state control. Its outputs are always active (noninverting buffers). However, the IOFF feature ensures near-zero I/O leakage (<10 µA) when VCC = 0 V, providing functional isolation during power-down - distinct from active tri-state but sufficient for many partial-power-down use cases.
Is the NL37WZ17USG pin-compatible with other TinyLogic® WZ series buffers?
The NL37WZ17USG uses the US8 package with fixed pinout (A1/Y3/A2/GND/Y2/A3/Y1/VCC). While other WZ-series devices like NL37WZ07USG share the same package, their pin assignments differ (e.g., NL37WZ07USG has inverted outputs and different pin mapping), so they are not pin-compatible. Always verify pinout per datasheet before substitution.
What is the typical hysteresis voltage of the NL37WZ17USG at VCC = 3.3 V?
At VCC = 3.3 V, the NL37WZ17USG exhibits a typical hysteresis voltage (VH) of 0.93 V, calculated as VT+ − VT− = 2.2 V − 1.27 V (from DC Electrical Characteristics table). This value ensures strong noise margin for signals with slow edges or moderate EMI in industrial control applications.
Can the NL37WZ17USG be used in a 1.8 V system with 5 V-tolerant inputs from legacy peripherals?
Yes, the NL37WZ17USG is explicitly designed for 1.65 V to 5.5 V operation and supports 5.5 V-tolerant inputs even when VCC = 1.8 V. This allows direct connection to 5 V peripherals (e.g., older microcontrollers or sensors) without level shifters, provided output loads are compatible with 1.8 V logic levels - verified in the Recommended Operating Conditions and DC Electrical Characteristics sections.
NL37WZ17USG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 37WZ
- Package/Case:
- 8-VFSOP (0.091", 2.30mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 3
- Number of Bits per Element:
- 1
- Input Type:
- Schmitt Trigger
- Output Type:
- Push-Pull
- Current - Output High, Low:
- 32mA, 32mA
- Voltage - Supply:
- 2.3V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- US8
NL37WZ17USG FAQ
1.How can I place an order for NL37WZ17USG through Aetrix?
Please submit a Request for Quotation (RFQ) for NL37WZ17USG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NL37WZ17USG reliable?
The price and inventory of NL37WZ17USG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NL37WZ17USG is usually 5 days.
3.What payment methods are accepted for NL37WZ17USG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NL37WZ17USG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NL37WZ17USG?
NL37WZ17USG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NL37WZ17USG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NL37WZ17USG?
For technical support, including NL37WZ17USG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NL37WZ17USG requirements.
6.How does Aetrix verify that NL37WZ17USG is sourced from the original manufacturer or authorized distributors?
All NL37WZ17USG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NL37WZ17USG meets industry standards.
7.What is the process for return or replacement of NL37WZ17USG?
All NL37WZ17USG units undergo pre-shipment inspection (PSI). If there is an issue with NL37WZ17USG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NL37WZ17USG part is unused and in its original packaging.
Return procedure for NL37WZ17USG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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