onsemi NL37WZ17USG-L22190
- Part No.:
- NL37WZ17USG-L22190
- Manufacturer:
- onsemi
- Package:
- 8-VFSOP (0.091", 2.30mm Width)
- Datasheet:
-
NL37WZ17USG-L22190.pdf
- Description:
- IC BUFFER NON-INVERT 5.5V US8
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
NL37WZ17USG-L22190 from onsemi is a triple noninverting Schmitt-trigger buffer IC operating from 1.65 V to 5.5 V, delivering 3.2 ns typical propagation delay at 5 V, ±24 mA output drive at 3.0 V, and overvoltage-tolerant inputs/outputs up to 5.5 V - used in noise-immune signal conditioning for industrial sensor interfaces and level-shifting I/O buffers.
For engineers reviewing the NL37WZ17USG-L22190 datasheet, pinout, applications, or equivalent options, key selection criteria include Schmitt-trigger hysteresis (0.7 V typ. at 5.5 V), IOFF partial power-down support, US8 package footprint, and AEC-Q100 qualification for automotive-grade reliability.
Technical Context
The NL37WZ17USG-L22190 implements three independent noninverting Schmitt-trigger buffers with input hysteresis (VH = 0.7 V typ. at VCC = 5.5 V) and rail-to-rail output swing. It supports mixed-voltage system interfacing via overvoltage-tolerant inputs (up to 5.5 V) and IOFF circuitry enabling safe partial power-down operation when VCC = 0 V.
Its logic function is defined by a single-input/single-output per channel with no internal feedback beyond hysteresis; propagation delay varies with supply voltage (2.7 ns typ. at 5.0 V, 5.0 ns typ. at 3.3 V) and load capacitance (CL = 15 pF or 50 pF), and it exhibits low input capacitance (2.5 pF) and power dissipation capacitance (11 pF at 5.5 V).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.65 V to 5.5 V - enables interoperability across 1.8 V, 2.5 V, 3.3 V, and 5 V logic domains without level shifters. |
| tPD (Typ) | 3.2 ns at VCC = 5 V, CL = 15 pF - supports high-speed digital signal conditioning in timing-critical paths. |
| IOH/IOL | ±24 mA at VCC = 3.0 V - drives moderate capacitive loads and multiple CMOS inputs without external buffering. |
| VIN/VOUT Tolerance | Up to 5.5 V - allows connection to higher-voltage buses while powered from lower VCC, preventing damage during hot insertion. |
| Hysteresis (VH) | 0.7 V typical at VCC = 5.5 V - rejects noise up to ±350 mV on slow-rising/falling signals (e.g., mechanical switch debouncing). |
| IOFF Leakage | ≤10 µA at VCC = 0 V - isolates powered-down sections of a system, preventing back-powering and bus contention. |
| Operating Temp | −55 °C to +125 °C - qualified for under-hood automotive and extended-temperature industrial environments. |
Pinout & Package
Package: US8 (Case 493), 8-pin ultra-small surface-mount package with 0.5 mm pitch, 2.1 mm × 2.0 mm body size, and exposed pad not present.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (A1) | Input Channel 1 | Schmitt-trigger input for first buffer; accepts 0–5.5 V regardless of VCC level. |
| 2 (Y3) | Output Channel 3 | Noninverting buffered output corresponding to A3; driven high/low or tri-stated via IOFF. |
| 3 (A2) | Input Channel 2 | Schmitt-trigger input for second buffer; electrically identical to A1 and A3. |
| 4 (GND) | Ground Reference | Primary return path for all supply and signal currents; must be low-impedance for noise immunity. |
| 5 (Y2) | Output Channel 2 | Noninverting buffered output corresponding to A2; shares same drive strength and timing as Y1/Y3. |
| 6 (A3) | Input Channel 3 | Schmitt-trigger input for third buffer; fully independent with no internal coupling to A1/A2. |
| 7 (Y1) | Output Channel 1 | Noninverting buffered output corresponding to A1; matches AC/DC specs of Y2/Y3. |
| 8 (VCC) | Positive Supply | Single power rail for all three buffers; powers internal logic and output drivers; IOFF active when VCC = 0 V. |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger inputs with adjustable hysteresis | Hysteresis scales with VCC (0.15 V min at 1.65 V, 0.7 V typ. at 5.5 V), enabling robust noise rejection across voltage domains. |
| Overvoltage-tolerant I/O | Inputs and outputs withstand up to 5.5 V independently of VCC, supporting mixed-supply system interconnect without clamping diodes. |
| IOFF partial power-down protection | Outputs enter high-impedance state with ≤10 µA leakage when VCC = 0 V, preventing back-driving of powered subsystems. |
| High-speed propagation | 3.2 ns typical tPD at 5 V enables use in clock distribution, data strobing, and fast control signal routing. |
| AEC-Q100 qualified (-Q variant) | This NL37WZ17USG-L22190 marking indicates automotive-grade qualification (Grade 1, −40 °C to +125 °C ambient), PPAP-capable manufacturing. |
Applications
| Industrial Sensor Interface | Automotive Body Control Module |
|---|---|
|
Use Scenario: Conditioning noisy analog switch or encoder signals in factory automation PLC I/O modules. IC Role / Device Role / Timing Role: Schmitt-trigger buffer cleans slow-rising mechanical contact bounce and EMI-induced glitches before MCU GPIO sampling. Use Value: 0.7 V hysteresis at 5 V suppresses >350 mV noise spikes; 3.2 ns delay preserves real-time response for motion control loops. |
Use Scenario: Level-shifting and debouncing door lock actuator feedback signals in 12 V vehicle architectures. IC Role / Device Role / Timing Role: Interfaces 5 V microcontroller GPIO to 12 V load-sense lines while rejecting battery ripple and load dump transients. Use Value: 5.5 V input tolerance eliminates external clamping; AEC-Q100 qualification ensures reliability in under-dash thermal environments. |
| USB-C Port Power Management | Medical Diagnostic Equipment Front-End |
|
Use Scenario: Isolating CC line status detection logic from VBUS-powered USB-C port controllers during hot-plug events. IC Role / Device Role / Timing Role: Buffers CC pin voltage thresholds while maintaining isolation between 5 V controller domain and 20 V VBUS domain. Use Value: IOFF enables safe VCC = 0 V operation during port disconnect; overvoltage tolerance prevents latch-up during VBUS surge. |
Use Scenario: Debouncing emergency stop button inputs and optical encoder signals in portable ultrasound devices. IC Role / Device Role / Timing Role: Provides ESD-hardened, low-capacitance (2.5 pF) signal conditioning ahead of precision ADC sampling clocks. Use Value: 2.5 pF input capacitance minimizes signal distortion; −55 °C to +125 °C rating supports sterilization and battery-operated field use. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Schmitt-trigger buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G17DBVR | Single-channel only; 3.5 ns tPD at 3.3 V; no IOFF; max VCC = 5.5 V but VIN tolerance limited to VCC + 0.5 V. | Lacks partial power-down capability and overvoltage tolerance; suitable only for same-rail systems. | Select when board space is constrained and mixed-voltage isolation is not required. |
| MC74VHC1GT17DTT1G | Single-channel; 7.4 ns tPD at 3.3 V; IOFF supported; VIN tolerant to 5.5 V; AEC-Q100 qualified (Grade 2). | Slower propagation and single-channel limit throughput in multi-signal systems like encoder interfaces. | Prefer for cost-sensitive automotive applications where triple-channel density is unnecessary. |
Compared with SN74LVC1G17DBVR and MC74VHC1GT17DTT1G, the NL37WZ17USG-L22190 delivers triple-channel integration, faster 3.2 ns propagation at 5 V, and guaranteed 5.5 V overvoltage tolerance - making it optimal for compact, noise-prone, mixed-voltage industrial and automotive signal routing.
Availability
NL37WZ17USG-L22190 is available at Aetrix Electronics and suitable for industrial sensor interface, automotive body control, and medical diagnostic equipment requiring stable component supply and long-term lifecycle assurance.
Supply support for NL37WZ17USG-L22190 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier focused on energy-efficient electronics, serving automotive, industrial, cloud, and medical markets with discrete, analog, and logic solutions.
The NL37WZ17USG-L22190 belongs to onsemi's TinyLogic® WZ ultra-high-speed logic family, designed specifically for low-voltage, low-power, noise-immune signal conditioning in space-constrained and thermally demanding applications.
FAQ
What is the maximum input voltage the NL37WZ17USG-L22190 can tolerate when powered from 1.8 V?
The NL37WZ17USG-L22190 supports input voltages up to 5.5 V regardless of VCC level - meaning it safely accepts 5 V signals even when VCC = 1.8 V. This overvoltage tolerance eliminates external clamping components in mixed-voltage systems and is confirmed in the Absolute Maximum Ratings table (VIN = −0.5 V to +6.5 V) and Recommended Operating Conditions (VIN = 0 to 5.5 V).
Does the NL37WZ17USG-L22190 support true tri-state operation?
No, the NL37WZ17USG-L22190 does not feature an enable pin or active tri-state mode. Instead, it provides IOFF (power-off isolation): when VCC = 0 V, all outputs enter a high-impedance state with ≤10 µA leakage current. This protects downstream circuits during partial power-down but differs from conventional OE-controlled tri-state logic.
What is the typical hysteresis voltage of the NL37WZ17USG-L22190 at 3.3 V supply?
At VCC = 3.3 V, the NL37WZ17USG-L22190 exhibits a typical hysteresis voltage (VH) of 0.93 V, as specified in the DC Electrical Characteristics table. This value is derived from VT+ = 2.2 V and VT− = 1.27 V (typ.), yielding VH = VT+ − VT− = 0.93 V - sufficient to reject common-mode noise in industrial control signal paths.
Is the NL37WZ17USG-L22190 pin-compatible with other TinyLogic® WZ series buffers?
The NL37WZ17USG-L22190 uses the standard US8 (8-pin) package with fixed pinout (A1/Y3/A2/GND/Y2/A3/Y1/VCC). While other WZ-series triple buffers (e.g., NL37WZ32) share the same footprint, their logic functions differ - the NL37WZ17USG-L22190 is noninverting Schmitt-trigger only, so direct functional replacement requires verifying signal polarity and hysteresis requirements.
What packaging and marking information does "L22190" indicate for NL37WZ17USG-L22190?
"L22190" is the date and lot code per onsemi's marking convention: "L" = lot code prefix, "22" = year (2022), "190" = day-of-year (July 9, 2022). The full marking on the US8 package reads "LX" (device code) followed by "ALYW" (assembly location/year/week) and "XXM" (date code); "L22190" appears in tape-and-reel labeling per ordering documentation.
NL37WZ17USG-L22190 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 37WZ
- Package/Case:
- 8-VFSOP (0.091", 2.30mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 3
- Number of Bits per Element:
- 1
- Input Type:
- Schmitt Trigger
- Output Type:
- Push-Pull
- Current - Output High, Low:
- 32mA, 32mA
- Voltage - Supply:
- 1.65V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- US8
NL37WZ17USG-L22190 FAQ
1.How can I place an order for NL37WZ17USG-L22190 through Aetrix?
Please submit a Request for Quotation (RFQ) for NL37WZ17USG-L22190 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NL37WZ17USG-L22190 reliable?
The price and inventory of NL37WZ17USG-L22190 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NL37WZ17USG-L22190 is usually 5 days.
3.What payment methods are accepted for NL37WZ17USG-L22190?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NL37WZ17USG-L22190 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NL37WZ17USG-L22190?
NL37WZ17USG-L22190 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NL37WZ17USG-L22190 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NL37WZ17USG-L22190?
For technical support, including NL37WZ17USG-L22190 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NL37WZ17USG-L22190 requirements.
6.How does Aetrix verify that NL37WZ17USG-L22190 is sourced from the original manufacturer or authorized distributors?
All NL37WZ17USG-L22190 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NL37WZ17USG-L22190 meets industry standards.
7.What is the process for return or replacement of NL37WZ17USG-L22190?
All NL37WZ17USG-L22190 units undergo pre-shipment inspection (PSI). If there is an issue with NL37WZ17USG-L22190, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NL37WZ17USG-L22190 part is unused and in its original packaging.
Return procedure for NL37WZ17USG-L22190:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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