onsemi NLSV1T34AMX1TCG
- Part No.:
- NLSV1T34AMX1TCG
- Manufacturer:
- onsemi
- Package:
- 6-XFLGA
- Datasheet:
-
NLSV1T34AMX1TCG.pdf
- Description:
- IC TRANSLATOR UNIDIR 6ULLGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
NLSV1T34AMX1TCG from onsemi is a 1-bit dual-supply non-inverting level translator enabling bidirectional voltage translation between 0.9 V and 4.5 V domains. It features independent VCCA (input-side supply) and VCCB (output-side supply), power-off high-impedance I/O, and OVT protection to 4.5 V. Used in mobile phone baseband-to-RF interface logic, it supports low-power, space-constrained interconnects between disparate voltage rails.
For engineers reviewing the NLSV1T34AMX1TCG datasheet, pinout, applications, or equivalent options, key selection criteria include dual-rail sequencing tolerance, sub-2.5 ns propagation delay at 3.3 V, ultra-low static current (<4.0 µA), ULLGA6 package footprint (1.45 mm × 1.0 mm), and AEC-Q100 qualification for automotive edge nodes.
Technical Context
The NLSV1T34AMX1TCG implements passive, transistor-based level translation without internal voltage regulation or direction control pins. Its input (A) and output (B) stages are independently referenced to VCCA and VCCB, allowing asymmetric rail operation - e.g., 1.2 V MCU GPIO to 3.3 V sensor interface. No external biasing or pull-ups required.
It guarantees power-off protection: when either VCCA or VCCB = 0 V, both A and B terminals enter high-impedance state with leakage <5.0 µA. Input and output pins withstand 4.5 V regardless of supply state, satisfying I/O overvoltage tolerance requirements in mixed-voltage systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCCA / VCCB Range | 0.9 V to 4.5 V - enables direct interface between sub-1.2 V logic (e.g., LPDDR I/O) and 3.3 V peripherals without external regulators |
| tPLH / tPHL | 1.6 ns to 3.3 ns (VCCA = VCCB = 3.3 V) - supports >200 MHz data rates in serial control buses like I²C clock stretching or SPI command lines |
| II (Input Leakage) | ±1.0 µA max - ensures minimal loading on weak-drive sources such as microcontroller GPIOs in sleep mode |
| ICCA + ICCB | <4.0 µA max - allows integration into always-on sensor hubs with multi-year battery life |
| VIH / VIL Thresholds | VIL = 0.1×VCCA min; VIH = 0.9×VCCA min - provides robust noise margin across full supply range, even at 0.9 V |
| OVT Protection | 4.5 V on A and B pins - eliminates need for external clamping diodes when interfacing with legacy 5 V tolerant peripherals |
| ESD Rating | HBM >3000 V - meets IEC 61000-4-2 Level 3 for handheld device touchpoints and exposed connectors |
Pinout & Package
Package: ULLGA6 (Case 613AF), 1.45 mm × 1.0 mm, 0.5 mm pitch, Pb-free, bottom-exposed thermal pad optional. Pin 1 marked by microdot or "Q"/"M" code per top-side marking diagram.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCCA | Input port power supply | Bias reference for input buffer and level-shifting core; must be stable before A signal assertion |
| VCCB | Output port power supply | Sets VOH/VOL levels and drives B output stage; independent sequencing allowed vs. VCCA |
| GND | Digital ground return | Common reference for both sides; requires low-inductance connection to minimize ground bounce during switching |
| A | Input signal terminal | Accepts logic levels referenced to VCCA; tolerates up to 4.5 V regardless of VCCA state |
| B | Output signal terminal | Drives logic levels referenced to VCCB; maintains high-Z when VCCB = 0 V |
| NC | No-connect terminal | Internally unconnected; must remain floating or tied to GND per layout guidelines - not used for thermal relief |
Key Features
| Feature | Design Value |
|---|---|
| Non-preferential supply sequencing | VCCA and VCCB may power up/down in any order without latch-up or damage - eliminates sequencing circuitry in multi-rail PMIC designs |
| Power-off high-impedance I/O | Both A and B enter Hi-Z when either supply drops below 0.5 V - prevents back-driving powered subsystems during partial power-down |
| OVT protection to 4.5 V | Input and output pins tolerate 4.5 V DC regardless of VCCA/VCCB state - enables safe hot-plug of 3.3 V peripherals into 1.8 V systems |
| Ultra-low static current | Total ICCA + ICCB ≤ 4.0 µA across full temperature range - reduces quiescent load on coin-cell or energy-harvesting supplies |
| Sub-2.5 ns propagation delay | 1.6 ns typical at 3.3 V - meets timing budget for 100 MHz+ SPI clock lines and fast GPIO handshaking in portable SoC interfaces |
Applications
| Mobile Baseband–RF Interface | Automotive Camera Sensor Link |
|---|---|
|
Use Scenario: Translating control signals between a 1.2 V application processor and a 2.8 V RF transceiver in LTE/5G smartphones. IC Role / Device Role / Timing Role: Non-inverting level translator bridging asymmetric voltage domains with no direction control needed. Use Value: Eliminates discrete resistor-divider networks while maintaining <2 ns delay and supporting 200 MHz burst signaling. |
Use Scenario: Interfacing a 1.8 V ADAS SoC GPIO to a 3.3 V image sensor's reset and sync lines in AEC-Q100-compliant camera modules. IC Role / Device Role / Timing Role: Automotive-grade voltage translator ensuring reliable startup/shutdown sequencing across isolated power domains. Use Value: Provides guaranteed power-off isolation and HBM >3000 V ESD protection required for under-hood camera harness routing. |
| Wearable Sensor Hub | Industrial IoT Edge Node |
|
Use Scenario: Connecting a 0.9 V ultra-low-power MCU to multiple 1.8 V/3.3 V environmental sensors (accelerometer, humidity, temp) in hearables. IC Role / Device Role / Timing Role: Single-bit translator enabling flexible rail assignment per peripheral without dedicated level-shifters per interface. Use Value: Reduces BOM count and PCB area versus discrete solutions while consuming <4 µA total quiescent current. |
Use Scenario: Isolating 2.5 V industrial PLC I/O controller logic from 3.3 V communication ICs (RS-485 transceivers, CAN FD controllers) in harsh environments. IC Role / Device Role / Timing Role: Robust voltage translator with 4.5 V OVT tolerance and -40°C to +85°C operation for factory-floor signal conditioning. Use Value: Prevents field failures due to supply brownouts or transient overvoltages on shared backplane traces. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar level translation applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TXS0101DCKR | Single-bit auto-direction sensing; higher ICC (10 µA typ); SC-70-5 package (2.0 × 1.25 mm) | Requires no direction control but adds capacitive loading; less suitable for fixed-direction high-speed clocks | Prefer TXS0101DCKR only when bidirectional data lines (e.g., I²C SDA) require automatic direction detection |
| SN74AVC1T45DBVR | Direction-controlled (DIR pin); lower propagation delay (1.3 ns); same ULLGA6 footprint | Requires external DIR signal management; better for high-frequency unidirectional control lines where timing margin is critical | Choose SN74AVC1T45DBVR when precise control over signal direction and sub-1.5 ns delay outweigh sequencing flexibility |
Compared with TXS0101DCKR and SN74AVC1T45DBVR, the NLSV1T34AMX1TCG uniquely combines supply-agnostic sequencing, ultra-low ICC, and OVT protection in the smallest ULLGA6 footprint - making it optimal for space- and power-constrained fixed-direction interfaces where reliability under partial power loss is essential.
Availability
NLSV1T34AMX1TCG is available at Aetrix Electronics and suitable for mobile phone baseband–RF interconnects, automotive camera sensor links, wearable sensor hubs, industrial IoT edge nodes, and other applications requiring stable component supply with AEC-Q100 traceability and long-term lifecycle support.
Supply support for NLSV1T34AMX1TCG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier delivering energy-efficient, intelligent power and sensing solutions for automotive, industrial, cloud, medical, and IoT applications.
The NLSV1T34AMX1TCG belongs to onsemi's precision analog and interface product line, designed specifically for low-voltage, low-power, mixed-rail system-level signal translation in portable and automotive electronics.
FAQ
What is the maximum operating frequency supported by the NLSV1T34AMX1TCG?
The NLSV1T34AMX1TCG does not specify a maximum operating frequency directly, but its propagation delay (tPLH/tPHL) is 1.6 ns to 3.3 ns depending on supply voltage - enabling reliable operation up to ~200 MHz for digital control signals such as SPI clock or GPIO handshaking. Signal integrity depends on board layout, trace length, and load capacitance; for sustained high-speed data, ensure CL ≤ 15 pF per the AC test conditions.
Does the NLSV1T34AMX1TCG require external pull-up resistors on the A or B pins?
No, the NLSV1T34AMX1TCG does not require external pull-up resistors. Its internal architecture uses active MOSFET-based translation that functions correctly with driven CMOS inputs and outputs. Pull-ups are unnecessary unless the system design mandates weak bus termination - in which case, values must be selected to avoid exceeding the ±50 mA output drive limit specified in the datasheet.
Can VCCA and VCCB be set to the same voltage, such as 3.3 V, for use as a buffer in the NLSV1T34AMX1TCG?
Yes, the NLSV1T34AMX1TCG operates correctly with VCCA = VCCB = 3.3 V and functions as a low-delay, low-power non-inverting buffer. In this configuration, it delivers tPLH/tPHL ≈ 1.7 ns, ICCA + ICCB < 4.0 µA, and maintains full OVT protection and power-off isolation - making it suitable for replacing standard logic buffers in noise-sensitive or power-constrained locations.
Is the NLSV1T34AMX1TCG pin-compatible with other packages of the NLSV1T34 family?
No, the NLSV1T34AMX1TCG uses the ULLGA6 package (Case 613AF), which has a unique 6-pin layout with NC on pin 2. It is not pin-compatible with the SC-88A (5-pin) or UDFN6 (6-pin, different pinout) variants. Board redesign is required when migrating between packages - refer to the respective package drawings in the datasheet for mechanical and solder-mask requirements.
What is the meaning of the 'MX1' suffix in NLSV1T34AMX1TCG?
The 'MX1' suffix in NLSV1T34AMX1TCG denotes the ULLGA6 package variant (Case 613AF) with Pb-free finish and tape-and-reel packaging (3000 units/reel). It distinguishes this version from other NLSV1T34 offerings such as 'DFT2G' (SC-88A) or 'AMUTCG' (UDFN6, 1.45 × 1.0 mm). The 'A' prefix indicates standard commercial grade; 'NLV' would indicate automotive qualification.
NLSV1T34AMX1TCG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- -
- Package/Case:
- 6-XFLGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- Push-Pull
- Current - Output High, Low:
- 24mA, 24mA
- Voltage - Supply:
- 0.9V ~ 4.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-ULLGA (1.45x1)
NLSV1T34AMX1TCG FAQ
1.How can I place an order for NLSV1T34AMX1TCG through Aetrix?
Please submit a Request for Quotation (RFQ) for NLSV1T34AMX1TCG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NLSV1T34AMX1TCG reliable?
The price and inventory of NLSV1T34AMX1TCG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NLSV1T34AMX1TCG is usually 5 days.
3.What payment methods are accepted for NLSV1T34AMX1TCG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NLSV1T34AMX1TCG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NLSV1T34AMX1TCG?
NLSV1T34AMX1TCG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NLSV1T34AMX1TCG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NLSV1T34AMX1TCG?
For technical support, including NLSV1T34AMX1TCG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NLSV1T34AMX1TCG requirements.
6.How does Aetrix verify that NLSV1T34AMX1TCG is sourced from the original manufacturer or authorized distributors?
All NLSV1T34AMX1TCG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NLSV1T34AMX1TCG meets industry standards.
7.What is the process for return or replacement of NLSV1T34AMX1TCG?
All NLSV1T34AMX1TCG units undergo pre-shipment inspection (PSI). If there is an issue with NLSV1T34AMX1TCG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NLSV1T34AMX1TCG part is unused and in its original packaging.
Return procedure for NLSV1T34AMX1TCG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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