onsemi NLU1G86BMX1TCG
- Part No.:
- NLU1G86BMX1TCG
- Manufacturer:
- onsemi
- Category:
- Gates and Inverters
- Package:
- 6-XFLGA
- Datasheet:
-
NLU1G86BMX1TCG.pdf
- Description:
- IC GATE XOR 1CH 2-INP 6ULLGA
- Quantity:
- Payment:

- Shipping:

Inventory:147,000
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Product details
Overview
NLU1G86BMX1TCG from onsemi is a single 2-input exclusive OR (XOR) gate in ultra-small UDFN6 package (1.2 × 1.0 mm, 0.4 mm pitch), designed for high-speed logic-level translation and signal conditioning in space-constrained applications. It operates from 1.65 V to 5.5 V, delivers 3.5 ns typical propagation delay at 5.0 V, supports ±12.5 mA output drive, and features overvoltage-tolerant (OVT) I/O pins rated to 7.0 V independent of supply voltage - enabling robust interfacing in mixed-voltage systems such as portable IoT sensors and battery-powered microcontroller peripherals.
For engineers reviewing the NLU1G86BMX1TCG datasheet, pinout, applications, or equivalent options, key selection criteria include its OVT input tolerance, ultra-low quiescent current (1.0 µA max), guaranteed operation across −55°C to +125°C, and compatibility with 1.8 V / 3.3 V / 5 V logic families without level shifters.
Technical Context
The NLU1G86BMX1TCG implements standard CMOS XOR logic (Y = A ⊕ B) using advanced low-threshold transistors optimized for speed-power trade-off in miniaturized packages. Its input structure includes clamping diodes and ESD protection rated to >2000 V HBM, while output stages are symmetrically balanced to minimize skew between tPLH and tPHL.
It supports rail-to-rail digital input (0–5.5 V) and output (0–VCC) under all valid supply conditions (1.65–5.5 V), with latch-up immunity of ±500 mA per I/O at 125°C and power-down protection that prevents back-driving current when VCC = 0 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.65 V to 5.5 V - enables direct interface with 1.8 V, 3.3 V, and 5 V logic domains without external level translation. |
| tPD (Typ) | 3.5 ns @ VCC = 5.0 V, CL = 15 pF - ensures sub-4 ns timing for high-frequency control signals in real-time embedded systems. |
| IO Max | ±12.5 mA - sufficient to drive multiple standard CMOS inputs or small LEDs directly without buffer stages. |
| VIN/VOUT Tolerance | −0.5 V to +7.0 V - allows safe connection to higher-voltage buses or legacy interfaces without risk of damage during hot-swap or fault conditions. |
| ICC (Max) | 10 µA @ TA = 25°C - supports ultra-low-power sleep modes in battery-operated edge devices where standby current must remain below 1 µA system-wide. |
| Operating Temp | −55°C to +125°C - qualified for automotive under-hood, industrial motor control, and aerospace avionics environments. |
Pinout & Package
Package: UDFN6 (1.2 mm × 1.0 mm, 0.4 mm pitch, Case 517AA), Pb-free, moisture sensitivity level 1, with exposed thermal pad.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | GND | Ground reference for all internal circuitry and I/O; connects to PCB ground plane via exposed pad for thermal and EMI performance. |
| 2 | IN B | Second XOR input; overvoltage tolerant up to +7.0 V regardless of VCC state - supports mixed-supply signal routing. |
| 3 | IN A | Primary XOR input; identical electrical characteristics to Pin 2; both inputs share same VIH/VIL thresholds. |
| 4 | NC | No connect - internally unconnected; must be left floating or tied to GND per layout best practices to avoid parasitic coupling. |
| 5 | OUT Y | XOR logic output (Y = A ⊕ B); rail-to-rail swing, capable of sourcing/sinking ±12.5 mA into capacitive or resistive loads. |
| 6 | VCC | Positive supply input; decoupling capacitor (0.1 µF ceramic) required within 2 mm for stable high-speed switching. |
Key Features
| Feature | Design Value |
|---|---|
| Overvoltage-Tolerant I/O | Input and output pins withstand −0.5 V to +7.0 V continuously - eliminates need for external clamping diodes in mixed-voltage sensor hubs. |
| Power-Down Protection | Inputs remain high-impedance and non-backdriving when VCC = 0 V - prevents unintended current flow in partial-power-down system states. |
| Balanced Propagation Delays | tPLH and tPHL match within ±0.5 ns @ 5 V - critical for glitch-free clock gating and synchronous XOR-based encoding in data paths. |
| Ultra-Small Footprint | UDFN6 1.2 × 1.0 mm package saves >60% board area vs. SOT-363 - enables placement adjacent to BGA MCUs or within tight RF module layouts. |
Applications
| Industrial Sensor Interface | Low-Power Wearable Logic |
|---|---|
|
Use Scenario: Detecting differential motion signals from dual-axis MEMS accelerometers in predictive maintenance nodes. IC Role / Device Role / Timing Role: XOR gate compares inverted and non-inverted analog comparator outputs to generate zero-crossing pulses for event-triggered wake-up. Use Value: Enables sub-1 µA system sleep current by eliminating active comparators during idle periods, leveraging NLU1G86BMX1TCG's 1.0 µA ICC max and OVT inputs to tolerate sensor bias offsets. |
Use Scenario: Implementing simple parity generation for SPI command validation in hearable device firmware updates. IC Role / Device Role / Timing Role: Single XOR computes bit-wise parity across 8-bit command fields before flash write cycles to detect transmission corruption. Use Value: Reduces BOM count versus discrete transistor-based parity circuits while maintaining <4 ns timing margin for 10 MHz SPI clocks. |
| Automotive Body Control | USB-C Power Negotiation Logic |
|
Use Scenario: Generating window lift/drop direction signals from dual Hall-effect sensor inputs in door module ECUs. IC Role / Device Role / Timing Role: XOR resolves quadrature-encoded position transitions into directional control bits for H-bridge drivers. Use Value: Survives load-dump transients (up to +7.0 V) without protection components, meeting ISO 7637-2 Pulse 5a requirements in 12 V systems. |
Use Scenario: Detecting CC line polarity reversal during USB-C cable insertion to configure VCONN and power role negotiation. IC Role / Device Role / Timing Role: XOR compares CC1 and CC2 voltage states to determine plug orientation and initiate PD communication handshake. Use Value: Operates reliably across 3.3 V (PD controller) and 5 V (VBUS monitoring) domains due to OVT I/O, avoiding level-shifter ICs in compact Type-C receptacle designs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar XOR gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G86DBVR | Same 1.65–5.5 V range and 3.5 ns tPD, but only rated to 5.5 V I/O (not 7.0 V); no power-down protection. | Lacks overvoltage tolerance - requires external clamps if interfacing with >5.5 V signals; unsuitable for direct connection to automotive CAN/LIN stubs. | Select when cost is primary constraint and system operates strictly within 5 V domain with clean supply rails. |
| 74AUP1G86GW,125 | Lower ICC (0.9 µA typ), wider temp range (−40°C to +125°C), but slower tPD (6.2 ns @ 3.3 V); I/O rated to 3.6 V only. | Not suitable for 5 V logic or mixed-voltage interfaces; better for ultra-low-power 1.8 V/2.5 V mobile SoC subsystems where speed is secondary. | Prefer for battery-powered handhelds with strict 1 µA sleep budget and no need for >3.6 V signal handling. |
Compared with SN74LVC1G86DBVR and 74AUP1G86GW,125, the NLU1G86BMX1TCG uniquely combines 7.0 V OVT I/O, power-down protection, and sub-4 ns speed in a 1.2 × 1.0 mm footprint - making it the only choice for ruggedized, space-constrained XOR functions in automotive, industrial, and USB-C designs requiring mixed-voltage resilience.
Availability
NLU1G86BMX1TCG is available at Aetrix Electronics and suitable for industrial sensor interface, low-power wearable logic, and automotive body control applications requiring stable component supply, long-term lifecycle support, and consistent Pb-free UDFN6 packaging.
Supply support for NLU1G86BMX1TCG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier focused on energy-efficient technologies for automotive, industrial, cloud, medical, and IoT applications.
The NLU1G86BMX1TCG belongs to the MiniGate™ family of ultra-small logic ICs, engineered specifically for space-constrained, mixed-voltage embedded systems where traditional SOT packages cannot fit and overvoltage resilience is mandatory.
FAQ
What is the maximum input voltage the NLU1G86BMX1TCG can tolerate?
The NLU1G86BMX1TCG supports DC input voltages from −0.5 V to +7.0 V on all I/O pins, regardless of VCC level. This overvoltage tolerance is verified per JEDEC JESD78 latch-up testing and enables safe interfacing with higher-voltage subsystems without external protection components. The specification applies directly to the NLU1G86BMX1TCG and is not dependent on operating supply voltage.
Does the NLU1G86BMX1TCG require external pull-up or pull-down resistors on unused inputs?
No - the NLU1G86BMX1TCG has no internal pull resistors, but its inputs are CMOS-compatible and must be actively driven to a defined logic level. Leaving an input floating may cause excessive ICC or oscillation. For unused inputs, tie IN A or IN B to GND or VCC using short traces; do not rely on leakage currents. The NLU1G86BMX1TCG datasheet explicitly prohibits floating inputs in any operating condition.
Can the NLU1G86BMX1TCG operate at 1.65 V supply while driving a 15 pF load?
Yes - the NLU1G86BMX1TCG is fully specified down to 1.65 V VCC, with AC timing parameters including tPLH/tPHL guaranteed for CL = 15 pF across the full temperature range (−55°C to +125°C). At 1.65 V, propagation delay increases to 15.5 ns (max), which remains usable for low-speed control logic. This capability is confirmed in Table 3 of the official NLU1G86/D datasheet for the NLU1G86BMX1TCG variant.
Is the exposed thermal pad on the NLU1G86BMX1TCG package required to be soldered to ground?
Yes - the exposed pad (Pin A3 per Case 517AA drawing) must be soldered to a PCB ground plane for thermal dissipation and EMI suppression. Thermal resistance θJA drops from 220°C/W (no pad connection) to 145°C/W with proper 4×4 mm² copper pour and ≥4 thermal vias. The NLU1G86BMX1TCG datasheet specifies this as mandatory for reliable operation above 50°C ambient.
What is the meaning of "BMX1" in the NLU1G86BMX1TCG part number?
The "BMX1" suffix identifies the specific package variant: UDFN6 (1.2 × 1.0 mm, 0.4 mm pitch, Case 517AA) with Pb-free finish and tape-and-reel packaging (3000 units per reel). This distinguishes it from other variants like NLU1G86AMUTCG (1.45 × 1.0 mm) and NLU1G86CMUTCG (1.0 × 1.0 mm). The NLU1G86BMX1TCG marking is "1M" per the datasheet's Marking Diagrams section.
NLU1G86BMX1TCG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- MiniGate™
- Package/Case:
- 6-XFLGA
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Logic Type:
- XOR (Exclusive OR)
- Number of Circuits:
- 1
- Number of Inputs:
- 2
- Features:
- -
- Voltage - Supply:
- 1.65V ~ 5.5V
- Current - Quiescent (Max):
- 1 µA
- Current - Output High, Low:
- 8mA, 8mA
- Input Logic Level - Low:
- -
- Input Logic Level - High:
- -
- Max Propagation Delay @ V, Max CL:
- 8.8ns @ 5V, 50pF
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-ULLGA (1.2x1)
NLU1G86BMX1TCG FAQ
1.How can I place an order for NLU1G86BMX1TCG through Aetrix?
Please submit a Request for Quotation (RFQ) for NLU1G86BMX1TCG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NLU1G86BMX1TCG reliable?
The price and inventory of NLU1G86BMX1TCG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NLU1G86BMX1TCG is usually 5 days.
3.What payment methods are accepted for NLU1G86BMX1TCG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NLU1G86BMX1TCG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NLU1G86BMX1TCG?
NLU1G86BMX1TCG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NLU1G86BMX1TCG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NLU1G86BMX1TCG?
For technical support, including NLU1G86BMX1TCG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NLU1G86BMX1TCG requirements.
6.How does Aetrix verify that NLU1G86BMX1TCG is sourced from the original manufacturer or authorized distributors?
All NLU1G86BMX1TCG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NLU1G86BMX1TCG meets industry standards.
7.What is the process for return or replacement of NLU1G86BMX1TCG?
All NLU1G86BMX1TCG units undergo pre-shipment inspection (PSI). If there is an issue with NLU1G86BMX1TCG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NLU1G86BMX1TCG part is unused and in its original packaging.
Return procedure for NLU1G86BMX1TCG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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