onsemi NLU1G86CMX1TCG
- Part No.:
- NLU1G86CMX1TCG
- Manufacturer:
- onsemi
- Category:
- Gates and Inverters
- Package:
- 6-XFLGA
- Datasheet:
-
NLU1G86CMX1TCG.pdf
- Description:
- IC GATE XOR 1CH 2-INP 6ULLGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
NLU1G86CMX1TCG from onsemi is a single 2-input exclusive OR (XOR) gate in ultra-small UDFN6 (1.0 × 1.0 mm) package, designed for high-speed logic-level translation and signal conditioning in space-constrained applications. It operates from 1.65 V to 5.5 V, delivers 3.5 ns typical propagation delay at 5.0 V, supports ±12.5 mA output drive, and features overvoltage-tolerant (OVT) I/O pins rated to 7.0 V independent of supply voltage - enabling robust interfacing in mixed-voltage systems such as portable sensor nodes and battery-powered IoT edge devices.
For engineers reviewing the NLU1G86CMX1TCG datasheet, pinout, applications, or equivalent options, key selection criteria include its OVT input tolerance, ultra-compact 1.0 × 1.0 mm UDFN6 footprint, guaranteed operation across −55°C to +125°C, low ICC (≤10 µA max at 25°C), and compatibility with 1.8 V / 3.3 V / 5 V logic families without level shifters.
Technical Context
The NLU1G86CMX1TCG implements a standard CMOS XOR function using advanced MiniGate process technology optimized for speed and area efficiency. Its input structure includes integrated protection diodes and power-down immunity, allowing safe operation when inputs exceed VCC or drop below GND - critical for hot-swap and partial-power-down scenarios.
Propagation delays are balanced between tPLH and tPHL (≤10 ns max at 5.0 V, CL = 15 pF), and AC performance is specified across full temperature range (−55°C to +125°C) with defined input transition rates (0–20 ns/V). The device lacks internal pull-ups or pull-downs and requires external termination for open-bus or wired-OR configurations.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.65 V to 5.5 V - supports direct interface with 1.8 V, 3.3 V, and 5 V logic domains without level translation. |
| tPD (Typ) | 3.5 ns @ VCC = 5.0 V, CL = 15 pF - enables use in sub-100 MHz digital timing paths with predictable latency. |
| IO Max | ±12.5 mA - sufficient to drive standard CMOS loads or small capacitive buses (≤50 pF) directly. |
| VIN/VOUT Tolerance | −0.5 V to +7.0 V - allows safe connection to higher-voltage signals (e.g., 5 V sensors on 3.3 V MCU) without external clamping. |
| ICC (Max) | 10 µA @ TA = 25°C - ensures ultra-low static power in always-on monitoring circuits. |
| Operating Temp | −55°C to +125°C - qualified for automotive under-hood, industrial control, and extended-temperature embedded applications. |
| CIN | 10 pF - low input capacitance minimizes loading on preceding drivers and preserves signal integrity in high-speed routing. |
Pinout & Package
Package: UDFN6 (1.0 × 1.0 mm, 0.35 mm pitch), case 517BX, exposed thermal pad, Pb-free, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | GND | Ground reference for all internal circuitry and I/O; must be connected to system ground plane for ESD and noise immunity. |
| 2 | IN B | Second logic input; accepts TTL- or CMOS-compatible voltage levels up to 7.0 V regardless of VCC. |
| 3 | IN A | Primary logic input; electrically identical to IN B with same overvoltage tolerance and leakage specs. |
| 4 | NC | No connect - internally unconnected; must remain floating or grounded per layout guidelines (not tied to VCC). |
| 5 | OUT Y | XOR output; actively drives high/low with rail-to-rail swing and ±12.5 mA capability; OVT-rated to 7.0 V. |
| 6 | VCC | Positive supply; decoupling capacitor (0.1 µF ceramic) required within 2 mm of this pin for stable switching. |
Key Features
| Feature | Design Value |
|---|---|
| Overvoltage-Tolerant I/O | Inputs and outputs withstand −0.5 V to +7.0 V independent of VCC - eliminates need for external clamping diodes in mixed-supply systems. |
| Power-Down Input Protection | Inputs remain high-impedance and non-latching when VCC = 0 V - prevents back-driving and current injection during power sequencing. |
| Balanced Propagation Delays | tPLH and tPHL differ by ≤1 ns (typ) - ensures minimal duty-cycle distortion in clock or data inversion paths. |
| Ultra-Small Footprint | 1.0 × 1.0 mm UDFN6 package saves >60% board area vs. SOT-363 - ideal for wearables and miniaturized sensor modules. |
| ESD Robustness | HBM >2000 V - meets IEC 61000-4-2 Level 2 for system-level ESD immunity without additional protection components. |
Applications
| Industrial Sensor Interface | Automotive Body Control |
|---|---|
Use Scenario: Interfacing analog sensor output comparators (e.g., window comparator outputs) to an MCU GPIO that detects fault conditions via XOR logic. IC Role / Device Role / Timing Role: Logic-level combiner generating active-high alert when two complementary fault flags differ - indicating sensor disagreement or wiring fault. Use Value: Enables single-pin fault detection without MCU firmware overhead; OVT inputs tolerate 5 V comparator outputs while operating from 3.3 V MCU rail. | Use Scenario: Generating wake-up pulse for CAN transceiver when door lock/unlock switch state changes relative to ignition status. IC Role / Device Role / Timing Role: XOR gate comparing ignition ON/OFF signal with door switch state to produce edge-triggered enable pulse. Use Value: Eliminates need for microcontroller involvement in basic wake-up logic; operates reliably across −40°C to +125°C ambient. |
| Portable Medical Monitor | Smart Home Motion Detector |
Use Scenario: Combining PIR sensor output with ambient light sensor decision to suppress false triggers in daylight. IC Role / Device Role / Timing Role: Digital enable gate producing motion alert only when PIR is active AND ambient light is below threshold - implemented as XOR of inverted light signal and PIR signal. Use Value: Reduces system-level power consumption by disabling RF transmission until valid low-light motion event occurs. | Use Scenario: Debouncing mechanical reed switch inputs from window/door contacts before feeding to security controller. IC Role / Device Role / Timing Role: Edge-detection aid: XORing delayed and undelayed switch signal to generate clean, jitter-free pulse on contact closure/opening. Use Value: Provides hardware-level contact bounce suppression without software timers or additional RC networks. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar XOR gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G86DBVR | Same 1.65–5.5 V VCC range but no OVT - max VIN = VCC + 0.5 V; 5-pin SOT-23 package (larger footprint). | Lacks overvoltage tolerance - requires external clamping if interfacing >VCC signals; unsuitable for mixed-voltage hot-swap. | Select when board space permits SOT-23 and all signals stay within VCC ±0.5 V. |
| MC74VHC1G86DTT1G | Wider VCC range (2.0–5.5 V); no OVT; 5-pin TSOP-5 package; slightly slower (tPD = 7.5 ns typ @ 5 V). | Higher minimum VCC excludes 1.8 V operation; no overvoltage protection limits use in legacy 5 V subsystem integration. | Prefer for cost-sensitive industrial designs where 1.8 V support and OVT are not required. |
Compared with SN74LVC1G86DBVR and MC74VHC1G86DTT1G, the NLU1G86CMX1TCG uniquely combines 1.65 V operation, 7.0 V OVT I/O, and 1.0 × 1.0 mm footprint - making it the only choice for miniaturized, mixed-voltage, hot-swap-capable XOR logic in next-gen edge devices.
Availability
NLU1G86CMX1TCG is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive body electronics, and portable medical monitors requiring stable component supply, long-term lifecycle support, and guaranteed Pb-free compliance.
Supply support for NLU1G86CMX1TCG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier delivering energy-efficient, intelligent power and sensing solutions for automotive, industrial, cloud, medical, and IoT applications.
The NLU1G86CMX1TCG belongs to the MiniGate family of ultra-small, high-speed logic ICs engineered specifically for space-constrained, mixed-voltage embedded systems requiring robust signal integrity and simplified board design.
FAQ
What is the maximum input voltage the NLU1G86CMX1TCG can tolerate?
The NLU1G86CMX1TCG supports DC input voltages from −0.5 V to +7.0 V on all I/O pins, regardless of VCC level. This overvoltage tolerance is verified per datasheet maximum ratings and enables direct connection to 5 V signals even when powered from 1.8 V or 3.3 V, eliminating external clamping components. The NLU1G86CMX1TCG maintains functional integrity and avoids latch-up under these conditions per JESD78 testing.
Does the NLU1G86CMX1TCG require external pull-up or pull-down resistors?
No, the NLU1G86CMX1TCG does not integrate internal pull-up or pull-down resistors. Its inputs are high-impedance CMOS and must be actively driven or externally terminated in open-bus or wired-OR configurations. External resistors may be needed only for specific system-level noise immunity or default-state requirements - not for basic XOR functionality. The NLU1G86CMX1TCG datasheet specifies no pull devices in the DC electrical characteristics table.
What package type and dimensions does the NLU1G86CMX1TCG use?
The NLU1G86CMX1TCG uses the UDFN6 package (case 517BX) measuring 1.0 mm × 1.0 mm with 0.35 mm pitch and an exposed thermal pad. It has six terminals: VCC, GND, IN A, IN B, OUT Y, and NC. This footprint is documented in page 7 of the NLU1G86/D datasheet and is distinct from larger variants like NLU1G86MUTCG (1.2 × 1.0 mm) and NLU1G86AMUTCG (1.45 × 1.0 mm).
Can the NLU1G86CMX1TCG operate at 1.8 V supply voltage?
Yes, the NLU1G86CMX1TCG is fully specified to operate at VCC = 1.8 V (within the 1.65 V to 5.5 V range). At 1.8 V, VIH is 1.26 V min and VOL is 0.44 V max at IOL = 4 mA, ensuring reliable interfacing with 1.8 V logic families. Propagation delay increases to ~13 ns (max) at 1.8 V, CL = 15 pF, as confirmed in the AC electrical characteristics table of the NLU1G86CMX1TCG datasheet.
Is the NLU1G86CMX1TCG pin-compatible with other MiniGate XOR devices?
No - the NLU1G86CMX1TCG is not pin-compatible with other MiniGate XOR variants such as NLU1G86MUTCG or NLU1G86AMUTCG due to differing package dimensions and terminal spacing (0.35 mm vs. 0.4 mm vs. 0.5 mm pitch). While all share identical logic function and pin assignment order, the physical layout requires separate PCB footprints. The NLU1G86CMX1TCG's 1.0 × 1.0 mm UDFN6 (517BX) is mechanically distinct and must be laid out accordingly.
NLU1G86CMX1TCG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- MiniGate™
- Package/Case:
- 6-XFLGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- XOR (Exclusive OR)
- Number of Circuits:
- 1
- Number of Inputs:
- 2
- Features:
- -
- Voltage - Supply:
- 1.65V ~ 5.5V
- Current - Quiescent (Max):
- 1 µA
- Current - Output High, Low:
- 8mA, 8mA
- Input Logic Level - Low:
- -
- Input Logic Level - High:
- -
- Max Propagation Delay @ V, Max CL:
- 8.8ns @ 5V, 50pF
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-ULLGA (1x1)
NLU1G86CMX1TCG FAQ
1.How can I place an order for NLU1G86CMX1TCG through Aetrix?
Please submit a Request for Quotation (RFQ) for NLU1G86CMX1TCG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NLU1G86CMX1TCG reliable?
The price and inventory of NLU1G86CMX1TCG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NLU1G86CMX1TCG is usually 5 days.
3.What payment methods are accepted for NLU1G86CMX1TCG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NLU1G86CMX1TCG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NLU1G86CMX1TCG?
NLU1G86CMX1TCG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NLU1G86CMX1TCG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NLU1G86CMX1TCG?
For technical support, including NLU1G86CMX1TCG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NLU1G86CMX1TCG requirements.
6.How does Aetrix verify that NLU1G86CMX1TCG is sourced from the original manufacturer or authorized distributors?
All NLU1G86CMX1TCG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NLU1G86CMX1TCG meets industry standards.
7.What is the process for return or replacement of NLU1G86CMX1TCG?
All NLU1G86CMX1TCG units undergo pre-shipment inspection (PSI). If there is an issue with NLU1G86CMX1TCG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NLU1G86CMX1TCG part is unused and in its original packaging.
Return procedure for NLU1G86CMX1TCG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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