onsemi NLU1G86MUTCG
- Part No.:
- NLU1G86MUTCG
- Manufacturer:
- onsemi
- Category:
- Gates and Inverters
- Package:
- 6-UFDFN
- Datasheet:
-
NLU1G86MUTCG.pdf
- Description:
- IC GATE XOR 1CH 2-INP 6UDFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,407
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
NLU1G86MUTCG from onsemi is a single 2-input exclusive OR (XOR) gate in ultra-small UDFN6 (1.2 × 1.0 mm, 0.4 mm pitch) package, designed for high-speed logic-level translation and signal conditioning in space-constrained applications. It operates from 1.65 V to 5.5 V, delivers 3.5 ns typical propagation delay at 5.0 V, supports ±12.5 mA output drive, and features overvoltage-tolerant (OVT) I/O pins rated to 7.0 V - enabling robust interfacing with mixed-voltage systems such as IoT sensor nodes and portable power management circuits.
For engineers reviewing the NLU1G86MUTCG datasheet, pinout, applications, or equivalent options, key selection considerations include its OVT input/output capability, ultra-low quiescent current (1.0 µA typ), 125°C operating temperature range, UDFN6 footprint compatibility, and absence of internal pull-ups/pull-downs requiring external biasing in open-drain configurations.
Technical Context
The NLU1G86MUTCG implements standard CMOS XOR logic (Y = A ⊕ B) using advanced high-speed process technology optimized for low-capacitance switching. Its input structure includes ESD protection diodes and overvoltage tolerance independent of VCC, allowing safe operation when inputs exceed supply voltage up to 7.0 V.
Propagation delays are balanced between tPLH and tPHL, with 3.5 ns typical (CL = 15 pF, VCC = 5.0 V) and 4.4 ns typical (CL = 15 pF, VCC = 3.3 V). The device lacks internal termination or configurable logic modes - it functions strictly as a fixed-function, non-inverting XOR gate with no enable or output control pins.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.65 V to 5.5 V - supports direct interface with 1.8 V, 2.5 V, 3.3 V, and 5 V logic families without level shifters. |
| tPD (Typ) | 3.5 ns @ VCC = 5.0 V, CL = 15 pF - enables use in sub-100 MHz digital timing paths with predictable edge alignment. |
| IO | ±12.5 mA - sufficient to drive multiple 74LVC inputs or small capacitive loads (< 30 pF) without external buffering. |
| VIN/VOUT Max | −0.5 V to +7.0 V - allows hot-swap, mixed-rail, or fault-tolerant signaling where inputs may float above VCC. |
| ICC (Max) | 10 µA @ TA = 25°C - ensures negligible static power impact in battery-powered always-on subsystems. |
| Operating Temp | −55°C to +125°C - qualified for automotive under-hood, industrial motor control, and extended-temperature embedded applications. |
Pinout & Package
Package: UDFN6 (1.2 mm × 1.0 mm, 0.4 mm pitch), exposed thermal pad, Pb-free, moisture sensitivity level 1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | GND | Ground reference for all I/O and internal circuitry; must be connected to system ground plane for ESD and noise immunity. |
| 2 | IN B | Second logic input; accepts DC voltages from −0.5 V to +7.0 V regardless of VCC; no internal pull-up/down. |
| 3 | IN A | First logic input; electrically identical to Pin 2; XOR function requires both inputs driven to defined logic levels. |
| 4 | NC | No connect - internally unconnected; must remain floating or grounded per layout best practices (not tied to VCC). |
| 5 | OUT Y | CMOS-compatible XOR output; actively drives high/low; supports rail-to-rail swing and fan-out to ≥10 LVC loads. |
| 6 | VCC | Positive supply; powers internal logic and output stage; bypass capacitor (0.1 µF) required within 2 mm of this pin. |
Key Features
| Feature | Design Value |
|---|---|
| Overvoltage-Tolerant I/O | Input and output pins withstand −0.5 V to +7.0 V independent of VCC, eliminating need for external clamping diodes in mixed-voltage domains. |
| Ultra-Small Footprint | UDFN6 package (1.2 × 1.0 mm) reduces PCB area by >60% vs. SOT-363, critical for wearables and miniaturized sensor modules. |
| Balanced Propagation Delays | tPLH and tPHL match within 0.3 ns (typ) at 5 V, minimizing duty-cycle distortion in clocked XOR applications like phase detection. |
| Power-Down Input Protection | Inputs remain protected and leakage-limited (< ±1.0 µA) even when VCC = 0 V, enabling safe partial-power-down system states. |
| Pb-Free & RoHS Compliant | Meets J-STD-609 Category 1 marking; compatible with lead-free reflow profiles up to 260°C peak temperature. |
Applications
| Motor Control Feedback | IoT Sensor Interface |
|---|---|
|
Use Scenario: Detect direction change in quadrature-encoded rotary encoder signals from BLDC motor position sensors. IC Role / Device Role / Timing Role: XOR gate computes phase difference between A and B channels to generate UP/DOWN pulses for counter ICs. Use Value: 3.5 ns propagation delay ensures accurate edge alignment at encoder speeds up to 500 kRPM; OVT inputs tolerate encoder cable ESD transients. |
Use Scenario: Condition analog sensor outputs digitized by low-power SAR ADCs before transmission via BLE or LoRaWAN. IC Role / Device Role / Timing Role: Logic-level translator and signal combiner that merges status flags (e.g., motion + temp alert) into single interrupt line. Use Value: 1.65–5.5 V operation allows direct interface with 1.8 V ADCs and 3.3 V radio SoCs; 10 µA max ICC extends battery life in multi-year deployments. |
| Automotive Body Electronics | Industrial PLC Input Conditioning |
|
Use Scenario: Debounce mechanical switch inputs (e.g., door latch, seatbelt buckle) in 12 V vehicle body control modules. IC Role / Device Role / Timing Role: XOR-based edge detector generating clean rising/falling pulses from noisy switch transitions. Use Value: −55°C to +125°C rating meets AEC-Q100 Grade 2 requirements; 7.0 V OVT tolerance accommodates load-dump transients without external protection. |
Use Scenario: Isolate and synchronize discrete field inputs (e.g., limit switches, safety interlocks) before feeding to FPGA-based logic controllers. IC Role / Device Role / Timing Role: Signal integrity enhancer that eliminates contact bounce and provides deterministic timing for programmable logic inputs. Use Value: Balanced tPLH/tPHL ensures consistent pulse width generation; UDFN6 footprint enables dense I/O expansion on modular PLC carrier boards. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar XOR gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G86DBVR | Same 1.65–5.5 V VCC, but SOT-363 (2.1 × 1.25 mm) package; tPD = 4.5 ns (typ); no OVT - max VIN = VCC + 0.5 V. | Requires external clamping for >VCC inputs; larger footprint limits use in ultra-dense layouts. | Select when board space permits and system rails are tightly regulated with no overvoltage risk. |
| 74AUP1G86GW,125 | Lower VCC range (0.8–3.6 V); tPD = 6.3 ns (typ); IO = ±4 mA; OVT not specified - max VIN = VCC + 0.3 V. | Not suitable for 5 V systems or mixed-rail interfaces; insufficient drive for LVC fan-out. | Select only for sub-3.3 V battery-powered designs where ultra-low ICC (0.9 µA) outweighs speed and voltage margin trade-offs. |
Compared with SN74LVC1G86DBVR and 74AUP1G86GW,125, the NLU1G86MUTCG uniquely combines 7.0 V overvoltage tolerance, 1.2 × 1.0 mm UDFN6 packaging, and 3.5 ns speed - making it the only option among the three qualified for harsh mixed-voltage environments with strict size constraints.
Availability
NLU1G86MUTCG is available at Aetrix Electronics and suitable for motor control feedback, IoT sensor interface, and automotive body electronics requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for NLU1G86MUTCG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier focused on energy-efficient innovation for automotive, industrial, cloud, medical, and IoT applications.
The NLU1G86MUTCG belongs to the MiniGate family of ultra-small logic devices engineered specifically for space-constrained, high-reliability embedded systems requiring robust voltage handling and minimal PCB footprint.
FAQ
What logic function does the NLU1G86MUTCG implement?
The NLU1G86MUTCG implements a standard 2-input exclusive OR (XOR) Boolean function: Y = A ⊕ B. When inputs A and B differ (one high, one low), the output Y is high; when they match (both high or both low), Y is low. This behavior is fixed and cannot be reconfigured - the NLU1G86MUTCG contains no mode pins, registers, or programmable elements.
Does the NLU1G86MUTCG require external pull-up or pull-down resistors on its inputs?
No, the NLU1G86MUTCG does not include internal pull-up or pull-down resistors, and its inputs are not weakly biased. External resistors are required only if the application demands a defined logic state during power-up, reset, or high-impedance source conditions. The NLU1G86MUTCG itself draws < ±1.0 µA input leakage across its full operating range.
Can the NLU1G86MUTCG operate with a 1.8 V supply and interface safely with 5 V signals?
Yes - the NLU1G86MUTCG supports VCC as low as 1.65 V and features overvoltage-tolerant (OVT) inputs and outputs rated to −0.5 V to +7.0 V. This means it can accept 5 V signals while powered from 1.8 V without damage or level-shifting components, making the NLU1G86MUTCG ideal for mixed-voltage signal conditioning.
What is the maximum capacitive load the NLU1G86MUTCG can drive reliably?
The NLU1G86MUTCG is characterized up to 50 pF load capacitance in its AC electrical specifications, with propagation delay increasing from 3.5 ns (CL = 15 pF) to 4.2 ns (CL = 50 pF) at 5.0 V. For reliable signal integrity beyond 50 pF, external buffering is recommended - the NLU1G86MUTCG's ±12.5 mA output drive is optimized for typical logic fan-out, not transmission-line driving.
Is the exposed pad on the NLU1G86MUTCG's UDFN6 package electrically connected?
Yes - the exposed thermal pad on the NLU1G86MUTCG's UDFN6 package is internally connected to GND (Pin 1) and must be soldered to a PCB ground plane for optimal thermal performance and ESD robustness. Thermal resistance θJA is specified assuming proper pad connection; omitting this connection degrades junction temperature rise by >25°C under continuous operation.
NLU1G86MUTCG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- MiniGate™
- Package/Case:
- 6-UFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- XOR (Exclusive OR)
- Number of Circuits:
- 1
- Number of Inputs:
- 2
- Features:
- -
- Voltage - Supply:
- 1.65V ~ 5.5V
- Current - Quiescent (Max):
- 1 µA
- Current - Output High, Low:
- 8mA, 8mA
- Input Logic Level - Low:
- -
- Input Logic Level - High:
- -
- Max Propagation Delay @ V, Max CL:
- 8.8ns @ 5V, 50pF
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-UDFN (1.2x1)
NLU1G86MUTCG FAQ
1.How can I place an order for NLU1G86MUTCG through Aetrix?
Please submit a Request for Quotation (RFQ) for NLU1G86MUTCG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NLU1G86MUTCG reliable?
The price and inventory of NLU1G86MUTCG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NLU1G86MUTCG is usually 5 days.
3.What payment methods are accepted for NLU1G86MUTCG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NLU1G86MUTCG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NLU1G86MUTCG?
NLU1G86MUTCG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NLU1G86MUTCG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NLU1G86MUTCG?
For technical support, including NLU1G86MUTCG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NLU1G86MUTCG requirements.
6.How does Aetrix verify that NLU1G86MUTCG is sourced from the original manufacturer or authorized distributors?
All NLU1G86MUTCG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NLU1G86MUTCG meets industry standards.
7.What is the process for return or replacement of NLU1G86MUTCG?
All NLU1G86MUTCG units undergo pre-shipment inspection (PSI). If there is an issue with NLU1G86MUTCG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NLU1G86MUTCG part is unused and in its original packaging.
Return procedure for NLU1G86MUTCG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NLU1G86MUTCG Tags
-
SN74LVC1G14DBVR
Texas Instruments
-
SN74LVC1G14DCKR
Texas Instruments
-
SN74AHC1G14DBVR
Texas Instruments
-
SN74LVC1G08DBVR
Texas Instruments
-
SN74LVC1G08DCKR
Texas Instruments
-
SN74LVC1G32DCKR
Texas Instruments
-
SN74LVC1G04DBVR
Texas Instruments
.jpg)
-
74LVC1G08GW,125
Nexperia USA Inc.
-
SN74LVC1G04DCKR
Texas Instruments
-
SN74AHC1G08DBVR
Texas Instruments
-
SN74LVC1G32DBVR
Texas Instruments
-
SN74AHCT1G08DBVR
Texas Instruments
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
