onsemi NLU1GT125MUTCG
- Part No.:
- NLU1GT125MUTCG
- Manufacturer:
- onsemi
- Package:
- 6-UFDFN
- Datasheet:
-
NLU1GT125MUTCG.pdf
- Description:
- IC BUFFER NON-INVERT 5.5V 6UDFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
NLU1GT125MUTCG from onsemi is a single-channel, non-inverting 3-state buffer with TTL-compatible inputs and full 5.0 V CMOS output swing, designed for level translation and bus isolation in space-constrained digital systems. It operates from 1.65 V to 5.5 V, delivers 3.8 ns typical propagation delay at 5.0 V, supports ±12.5 mA output drive, and features input/output overvoltage tolerance up to 7.0 V.
For engineers reviewing the NLU1GT125MUTCG datasheet, pinout, applications, or equivalent options, key selection factors include its UDFN6 (1.2 × 1.0 mm) ultra-small footprint, guaranteed 3-state leakage ≤ ±2.5 µA, AEC-Q100 qualification (NLV variant), and compatibility with both LSTTL and CMOS logic families across industrial temperature range (−55 °C to +125 °C).
Technical Context
The NLU1GT125MUTCG implements a single high-speed CMOS buffer with active-high 3-state enable (OE), where OE = High places Y in high-impedance state. Its input structure accepts TTL-level thresholds (VIL = 0.8 V, VIH = 2.0 V) while driving rail-to-rail CMOS outputs (VOH > 0.8 VCC, VOL < 0.1 VCC).
Input and output pins tolerate voltages up to 7.0 V independent of VCC, enabling robust hot-swap and mixed-voltage interface operation. Propagation delays (tPLH/tPHL) are balanced and specified down to 1.65 V supply, with dynamic power modeled via CPD = 14 pF at 5.0 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 1.65 V to 5.5 V - Enables interoperability across 1.8 V, 3.3 V, and 5 V logic domains |
| Propagation Delay (tPD) | 3.8 ns (typ) @ VCC = 5.0 V, CL = 15 pF - Supports >100 MHz data rates in short-bus applications |
| Output Drive Strength | ±12.5 mA - Sufficient to drive four LSTTL loads or one 50 pF capacitive load |
| Input Voltage Tolerance | −0.5 V to +7.0 V - Allows safe interfacing with higher-voltage peripherals without level shifters |
| 3-State Leakage (IOZ) | ±2.5 µA (max) @ TA = −55 °C to +125 °C - Ensures low standby current in multiplexed bus architectures |
| Operating Temperature | −55 °C to +125 °C - Qualified for extended industrial and automotive under-hood environments |
| Package | UDFN6, 1.2 × 1.0 mm, 0.4 mm pitch - Optimized for PCB area savings in portable and dense IoT modules |
Pinout & Package
Package: UDFN6 (1.2 mm × 1.0 mm, 0.4 mm pitch), no exposed pad, RoHS-compliant Pb-free construction.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | GND | Ground reference for all I/O and internal circuitry; must be connected to system ground plane |
| 2 | OE | Active-high 3-state enable input; drives output Y to high-impedance when logic High |
| 3 | IN A | Non-inverting data input; accepts TTL-compatible thresholds and tolerates up to 7.0 V |
| 4 | NC | No-connect terminal; left unconnected per design - not internally bonded |
| 5 | OUT Y | Inverted-output buffer stage; delivers full CMOS swing and ±12.5 mA drive capability |
| 6 | VCC | Positive supply input; decoupling capacitor (0.1 µF) required within 2 mm of this pin |
Key Features
| Feature | Design Value |
|---|---|
| TTL-Compatible Inputs | VIL = 0.8 V / VIH = 2.0 V threshold ensures direct connection to legacy LSTTL outputs without external biasing |
| Overvoltage-Tolerant I/O | Input and output pins withstand −0.5 V to +7.0 V regardless of VCC - eliminates need for external clamping diodes |
| Ultra-Small UDFN6 Footprint | 1.2 × 1.0 mm body size reduces PCB area by >60% vs. standard SOT-363, critical for wearables and sensor nodes |
| Balanced Propagation Delays | tPLH and tPHL match within 0.3 ns @ 5.0 V - minimizes skew in timing-critical control paths |
| Power-Down Input Protection | Inputs remain protected and leakage-limited even when VCC = 0 V - enables safe partial-power-down system states |
Applications
| Industrial Sensor Interface | Automotive Body Control Module |
|---|---|
|
Use Scenario: Isolating analog sensor ADC interface lines from noisy microcontroller buses in factory automation PLCs. IC Role / Device Role / Timing Role: Non-inverting 3-state buffer providing bidirectional signal integrity and voltage-level bridging between 3.3 V MCU and 5 V sensor front-end. Use Value: Prevents bus contention during ADC conversion cycles while maintaining sub-4 ns timing margin for 25 MHz SPI clock edges. |
Use Scenario: Enabling/disabling CAN transceiver control signals in vehicle door module ECUs with shared power rails. IC Role / Device Role / Timing Role: OE-controlled buffer isolating wake-up interrupt lines from main MCU during sleep mode to reduce quiescent current. Use Value: Achieves <1 µA system sleep current via guaranteed IOZ ≤ ±2.5 µA and zero-VCC input protection. |
| Portable Medical Wearable | IoT Edge Node Data Aggregation |
|
Use Scenario: Level-shifting GPIOs between ultra-low-power 1.8 V BLE SoC and 3.3 V environmental sensor array. IC Role / Device Role / Timing Role: Single-channel non-inverting buffer supporting dual-supply operation with rail-to-rail output swing. Use Value: Eliminates discrete level shifter components, saving 1.5 mm² PCB area and reducing BOM count in compact wearable form factor. |
Use Scenario: Multiplexing multiple UART debug ports onto a single FTDI USB-to-serial interface in smart meter gateways. IC Role / Device Role / Timing Role: 3-state bus buffer enabling time-division sharing of TX/RX lines among three subsystems. Use Value: Enables deterministic 3.8 ns propagation delay and <10 ns enable/disable timing for reliable 1 Mbps UART handshaking. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar non-inverting 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G125DBVR | Same 1.65–5.5 V range and UDFN6 package, but lacks 7.0 V overvoltage tolerance; IOZ = ±10 µA (max) | Not qualified for automotive AEC-Q100; rated only to +85 °C ambient | Select when cost sensitivity outweighs overvoltage robustness and extended temperature requirements |
| 74LVC1G125GW,125 | Identical logic function and 7.0 V tolerant I/O, but uses larger SOT-353 (2.1 × 1.25 mm) package | Higher board area consumption; same industrial temp range but no AEC-Q100 documentation | Select when UDFN6 assembly capability is unavailable and 1.2× area penalty is acceptable |
Compared with SN74LVC1G125DBVR and 74LVC1G125GW,125, the NLU1GT125MUTCG uniquely combines AEC-Q100 qualification, 7.0 V overvoltage tolerance, and the smallest UDFN6 footprint (1.2 × 1.0 mm), making it optimal for space- and reliability-critical automotive and industrial edge nodes.
Availability
NLU1GT125MUTCG is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive body control modules, portable medical wearables, and IoT edge node data aggregation requiring stable component supply and long-term lifecycle support.
Supply support for NLU1GT125MUTCG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier delivering energy-efficient, intelligent power and sensing solutions for automotive, industrial, cloud, medical, and IoT applications.
The NLU1GT125MUTCG belongs to the MiniGate™ family of ultra-small logic devices, engineered specifically for space-constrained, high-reliability digital interfacing in harsh-environment applications including automotive under-hood and industrial automation.
FAQ
What is the maximum operating voltage for NLU1GT125MUTCG inputs and outputs?
The NLU1GT125MUTCG inputs and outputs are rated for −0.5 V to +7.0 V, independent of VCC supply voltage. This overvoltage tolerance allows safe interfacing with higher-voltage peripherals without external protection components. The specification is verified per JEDEC JESD78 latch-up testing and applies across the full −55 °C to +125 °C operating temperature range. This feature is explicitly confirmed in the Maximum Ratings table of the official NLU1GT125/D datasheet.
Does NLU1GT125MUTCG support 1.8 V logic systems?
Yes, NLU1GT125MUTCG fully supports 1.8 V logic systems: its recommended operating supply range starts at 1.65 V, and it guarantees TTL-compatible input thresholds (VIL = 0.53 V, VIH = 1.4 V min) and CMOS output swing (VOH > 1.44 V, VOL < 0.18 V) at VCC = 1.8 V. These values are specified in the DC Electrical Characteristics table for TA = 25 °C and across temperature extremes, confirming interoperability with 1.8 V microcontrollers and FPGAs.
What is the thermal performance of NLU1GT125MUTCG in its UDFN6 package?
The NLU1GT125MUTCG in UDFN6 (1.2 × 1.0 mm) has a junction-to-ambient thermal resistance (θJA) of 230 °C/W when mounted on a standard 2-layer FR4 board with minimum copper pad spacing. Its maximum junction temperature is rated at 150 °C, and it operates reliably from −55 °C to +125 °C ambient. These thermal parameters are validated per JEDEC JESD51-2 and documented in the Thermal Characteristics section of the NLU1GT125/D datasheet.
Is NLU1GT125MUTCG pin-compatible with other MiniGate buffers?
No, NLU1GT125MUTCG is not pin-compatible with other MiniGate buffers such as NLU1GT04 or NLU1GT32 due to differing pin assignments and functional configurations. Its UDFN6 pinout (GND, OE, IN A, NC, OUT Y, VCC) is unique to the 1-channel non-inverting 3-state buffer function. Pin compatibility is neither claimed nor verified in the NLU1GT125/D datasheet, and substitution requires PCB layout revision.
What does the "MUTCG" suffix indicate in NLU1GT125MUTCG?
The "MUTCG" suffix denotes a specific packaging and compliance configuration: "MU" = UDFN6 package, "T" = tape-and-reel packaging, "C" = Pb-free (RoHS-compliant), and "G" = halogen-free. This ordering code corresponds to the 1.2 × 1.0 mm, 0.4 mm pitch UDFN6 variant shipped in 3000-unit reels, as defined in the Ordering Information table on page 4 of the NLU1GT125/D datasheet.
NLU1GT125MUTCG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- MiniGate™
- Package/Case:
- 6-UFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 1.65V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-UDFN (1.2x1)
NLU1GT125MUTCG FAQ
1.How can I place an order for NLU1GT125MUTCG through Aetrix?
Please submit a Request for Quotation (RFQ) for NLU1GT125MUTCG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NLU1GT125MUTCG reliable?
The price and inventory of NLU1GT125MUTCG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NLU1GT125MUTCG is usually 5 days.
3.What payment methods are accepted for NLU1GT125MUTCG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NLU1GT125MUTCG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NLU1GT125MUTCG?
NLU1GT125MUTCG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NLU1GT125MUTCG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NLU1GT125MUTCG?
For technical support, including NLU1GT125MUTCG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NLU1GT125MUTCG requirements.
6.How does Aetrix verify that NLU1GT125MUTCG is sourced from the original manufacturer or authorized distributors?
All NLU1GT125MUTCG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NLU1GT125MUTCG meets industry standards.
7.What is the process for return or replacement of NLU1GT125MUTCG?
All NLU1GT125MUTCG units undergo pre-shipment inspection (PSI). If there is an issue with NLU1GT125MUTCG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NLU1GT125MUTCG part is unused and in its original packaging.
Return procedure for NLU1GT125MUTCG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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