onsemi NLU1GT126MUTCG
- Part No.:
- NLU1GT126MUTCG
- Manufacturer:
- onsemi
- Package:
- 6-UFDFN
- Datasheet:
-
NLU1GT126MUTCG.pdf
- Description:
- IC BUFFER NON-INVERT 5.5V 6UDFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,100
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
NLU1GT126MUTCG from onsemi is a single-channel, non-inverting 3-state buffer IC with TTL-compatible inputs and full 5.0 V CMOS output swing, designed for signal routing in space-constrained digital systems. It operates from 1.65 V to 5.5 V, delivers 3.8 ns typical propagation delay at 5.0 V, supports ±12.5 mA output drive, and features input/output overvoltage tolerance up to 7.0 V - enabling robust interfacing between mixed-voltage logic domains in industrial control modules.
For engineers reviewing the NLU1GT126MUTCG datasheet, pinout, applications, or equivalent options, key selection considerations include its UDFN6 (1.2 × 1.0 mm) ultra-small footprint, OE-controlled 3-state operation, LSTTL-compatible input thresholds (VIL = 0.8 V, VIH = 2.0 V), and guaranteed 125 °C operating temperature capability.
Technical Context
The NLU1GT126MUTCG implements a single high-speed CMOS buffer stage with active-low 3-state enable (OE), where logic high on OE disables the output into high-impedance mode. Its input structure includes clamping diodes and ESD protection rated to ±500 mA latch-up immunity per JESD78.
Output drive is rail-to-rail (VOH > 0.8 VCC, VOL < 0.1 VCC under load), and both input and output pins tolerate 7.0 V regardless of VCC - supporting hot-swap and level-shifting use cases without external components. Propagation delays (tPLH/tPHL) and enable/disable times (tPZL/tPLZ) are characterized across 1.65–5.5 V supply and −55 °C to +125 °C ambient.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.65 V to 5.5 V - enables interoperability across 1.8 V, 3.3 V, and 5 V logic families without level shifters. |
| tPD (Typ) | 3.8 ns @ VCC = 5.0 V, CL = 15 pF - supports >100 MHz data rates in point-to-point signal paths. |
| IO Max | ±12.5 mA - sufficient to drive standard 50 pF loads or multiple 74LVC inputs without fanout limitation. |
| VIN Tolerance | −0.5 V to +7.0 V - allows safe connection to higher-voltage buses or unpowered subsystems during power sequencing. |
| Operating Temp | −55 °C to +125 °C - qualified for under-hood automotive, industrial motor drives, and outdoor telecom equipment. |
| Package | UDFN6, 1.2 × 1.0 mm, 0.4 mm pitch - reduces PCB area by >60% vs. SOT-363 while maintaining thermal performance. |
| MSL Level | Level 1 (unlimited floor life) - simplifies manufacturing handling and eliminates bake requirements prior to reflow. |
Pinout & Package
Package: UDFN6 (1.2 mm × 1.0 mm × 0.5 mm), case 517AA, Pb-free, bottom-exposed thermal pad (no internal connection). Pin 1 marked by chamfered corner; pin numbering follows standard UDFN counter-clockwise sequence.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | GND | Ground reference for all I/O and internal circuitry; must be connected to low-impedance system ground plane. |
| 2 | OE | Active-low 3-state enable input; logic low enables output buffer, logic high places Y in high-impedance state. |
| 3 | IN A | Non-inverting data input; accepts TTL-level thresholds (VIL ≤ 0.8 V, VIH ≥ 2.0 V) across full VCC range. |
| 4 | NC | No internal connection; left floating or tied to GND per layout best practice to reduce parasitic coupling. |
| 5 | OUT Y | Inverted logic not applied - output replicates IN A when enabled; full CMOS swing (0 V to VCC) with 12.5 mA sink/source. |
| 6 | VCC | Positive supply input; bypass capacitor (100 nF ceramic) required within 2 mm of this pin for stable high-speed operation. |
Key Features
| Feature | Design Value |
|---|---|
| LSTTL-Compatible Inputs | Guaranteed VIH ≥ 2.0 V and VIL ≤ 0.8 V at VCC = 5.0 V - ensures reliable interface with legacy 74LS/74ALS logic without pull-ups. |
| Overvoltage-Tolerant I/O | Withstands −0.5 V to +7.0 V on IN A and OUT Y independent of VCC - eliminates need for external clamping diodes in mixed-supply systems. |
| Ultra-Fast Enable/Disable | tPZL/tPLZ = 4.8 ns (typ) @ 5.0 V - enables precise timing control in multiplexed bus architectures with minimal dead-time overhead. |
| Low Quiescent Current | ICC ≤ 2.0 µA (max) at TA = 25 °C - supports always-on monitoring circuits in battery-backed industrial sensors. |
| Thermal Robustness | Rated for TJ ≤ 150 °C and MSL Level 1 - suitable for reflow soldering and sustained operation in sealed enclosures without forced cooling. |
Applications
| Industrial PLC Backplane Interface | Automotive Body Control Module |
|---|---|
|
Use Scenario: Isolating and buffering address/data lines between microcontroller and peripheral ASIC on a dense 4-layer PLC backplane. IC Role / Device Role / Timing Role: Non-inverting 3-state buffer enabling bidirectional bus sharing with precise OE-controlled contention avoidance. Use Value: 3.8 ns tPD and 4.8 ns tPZL ensure sub-10 ns timing margins for 50 MHz parallel bus cycles while UDFN6 saves >0.8 mm² per channel vs. SOT-363. |
Use Scenario: Level-shifting and signal conditioning between 3.3 V MCU GPIO and 5 V sensor cluster in door module electronics. IC Role / Device Role / Timing Role: Voltage-tolerant buffer translating logic levels without external resistors or MOSFETs, controlled via MCU GPIO. Use Value: 7.0 V input tolerance permits direct connection to 5 V sensor outputs even when MCU is unpowered, preventing back-drive damage. |
| Medical Diagnostic Equipment Data Link | Smart Energy Meter Communication Interface |
|
Use Scenario: Driving isolated SPI clock and data lines from an ARM Cortex-M4 to optocoupled transceivers in portable ultrasound units. IC Role / Device Role / Timing Role: Low-skew, rail-to-rail buffer ensuring clean edge integrity across isolation barrier with minimal added jitter. Use Value: Balanced tPLH/tPHL (≤0.5 ns skew) and 125 °C rating support continuous operation in thermally constrained handheld enclosures. |
Use Scenario: Enabling/disabling RS-485 transceiver drivers in DIN-rail mounted meters using microcontroller-controlled bus arbitration. IC Role / Device Role / Timing Role: 3-state gate controlling driver enable line to prevent bus contention during firmware updates or fault recovery. Use Value: OE-controlled high-Z state guarantees zero current leakage into disabled transceiver, meeting IEC 62056-21 low-power standby requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar non-inverting 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G126DBVR | Same UDFN6 package (1.45 × 1.0 mm), but 0.5 mm pitch; slightly higher ICC (10 µA max); identical VCC range and drive strength. | Marginally larger footprint; requires updated stencil aperture for assembly; same functional behavior in 3.3 V systems. | Select if existing design uses TI's 1.45 mm variant and board rework is impractical. |
| 74LVC1G125GW,125 | Inverting buffer (Y = NOT A); otherwise identical specs, package (TSSOP5), and temperature range. | Requires logic inversion in upstream firmware or external gate; unsuitable where signal polarity must be preserved. | Choose only when system architecture accommodates inverted control signals and TSSOP5 footprint is acceptable. |
Compared with SN74LVC1G126DBVR and 74LVC1G125GW,125, the NLU1GT126MUTCG offers the smallest PCB footprint (1.2 × 1.0 mm), lowest quiescent current (2 µA max), and superior overvoltage tolerance - making it optimal for miniaturized, mixed-voltage, and thermally demanding applications where pin-for-pin replacement is not required.
Availability
NLU1GT126MUTCG is available at Aetrix Electronics and suitable for industrial PLC backplanes, automotive body control modules, and medical diagnostic data links requiring stable component supply, long-term lifecycle support, and verified Pb-free compliance.
Supply support for NLU1GT126MUTCG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (Semiconductor Components Industries, LLC) is a global semiconductor supplier focused on energy-efficient technologies for automotive, industrial, cloud, medical, and IoT applications.
The MiniGate family - including NLU1GT126MUTCG - was engineered for ultra-compact, high-speed logic interfacing in thermally constrained and space-limited embedded systems, emphasizing low power, voltage tolerance, and manufacturability.
FAQ
What is the maximum operating temperature for the NLU1GT126MUTCG?
The NLU1GT126MUTCG is rated for continuous operation from −55 °C to +125 °C ambient temperature, with junction temperature limited to 150 °C. This specification is validated per JEDEC JESD22-A104 and applies across the full 1.65–5.5 V VCC range. The device maintains specified timing and DC parameters throughout this range, making NLU1GT126MUTCG suitable for under-hood automotive and industrial environments where thermal cycling is severe.
Does the NLU1GT126MUTCG require external pull-up or pull-down resistors on its inputs?
No, the NLU1GT126MUTCG does not require external pull-up or pull-down resistors on IN A or OE. Its inputs feature internal biasing that meets LSTTL-compatible thresholds (VIH ≥ 2.0 V, VIL ≤ 0.8 V at VCC = 5.0 V) without external components. However, OE should be actively driven - floating OE is undefined and may cause unintended output states. For fail-safe operation, tie OE to GND via a 10 kΩ resistor if not actively controlled.
Can the NLU1GT126MUTCG safely interface a 5 V sensor output with a 1.8 V microcontroller input?
Yes, the NLU1GT126MUTCG can safely interface a 5 V sensor output to a 1.8 V microcontroller input - but only when used as a level translator in the direction sensor → MCU. Its inputs tolerate up to 7.0 V regardless of VCC, so applying 5 V to IN A while VCC = 1.8 V is electrically safe. However, the output (OUT Y) swings from 0 V to VCC (1.8 V), which is compatible with 1.8 V logic inputs. Thus, NLU1GT126MUTCG enables robust 5 V-to-1.8 V unidirectional translation without external components.
What is the recommended PCB layout practice for the thermal pad on the NLU1GT126MUTCG UDFN6 package?
The NLU1GT126MUTCG UDFN6 package includes an exposed copper thermal pad on the bottom surface (case 517AA), which is not internally connected. Per onsemi's layout guidelines, this pad should be soldered to a dedicated thermal land on the PCB - typically a solid copper pour connected to GND via ≥4 thermal vias (0.3 mm diameter, spaced ≤1 mm apart). Do not connect the pad to VCC or leave it floating; proper grounding improves heat dissipation and reduces ground bounce during fast switching transitions of NLU1GT126MUTCG.
Is the NLU1GT126MUTCG pin-compatible with other devices in the NLU1GTxxx MiniGate family?
No, the NLU1GT126MUTCG is not pin-compatible with other NLU1GTxxx variants such as NLU1GT04 or NLU1GT32. While all share the UDFN6 footprint, pin assignments differ: NLU1GT126MUTCG uses pins 1=GND, 2=OE, 3=IN A, 4=NC, 5=OUT Y, 6=VCC; NLU1GT04 (inverter) assigns pin 2 to IN A and pin 5 to OE. Substituting without layout revision will result in incorrect functionality or damage. Always verify pin mapping against the specific device's datasheet before board reuse.
NLU1GT126MUTCG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- MiniGate™
- Package/Case:
- 6-UFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 1.65V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-UDFN (1.2x1)
NLU1GT126MUTCG FAQ
1.How can I place an order for NLU1GT126MUTCG through Aetrix?
Please submit a Request for Quotation (RFQ) for NLU1GT126MUTCG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NLU1GT126MUTCG reliable?
The price and inventory of NLU1GT126MUTCG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NLU1GT126MUTCG is usually 5 days.
3.What payment methods are accepted for NLU1GT126MUTCG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NLU1GT126MUTCG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NLU1GT126MUTCG?
NLU1GT126MUTCG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NLU1GT126MUTCG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NLU1GT126MUTCG?
For technical support, including NLU1GT126MUTCG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NLU1GT126MUTCG requirements.
6.How does Aetrix verify that NLU1GT126MUTCG is sourced from the original manufacturer or authorized distributors?
All NLU1GT126MUTCG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NLU1GT126MUTCG meets industry standards.
7.What is the process for return or replacement of NLU1GT126MUTCG?
All NLU1GT126MUTCG units undergo pre-shipment inspection (PSI). If there is an issue with NLU1GT126MUTCG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NLU1GT126MUTCG part is unused and in its original packaging.
Return procedure for NLU1GT126MUTCG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NLU1GT126MUTCG Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments

-
SN74LVC2G17DBVR
Texas Instruments

-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments

-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
