onsemi NLU2G06CMX1TCG
- Part No.:
- NLU2G06CMX1TCG
- Manufacturer:
- onsemi
- Category:
- Gates and Inverters
- Package:
- 6-XFLGA
- Datasheet:
-
NLU2G06CMX1TCG.pdf
- Description:
- IC INVERTER 2CH 2-INP 6ULLGA
- Quantity:
- Payment:

- Shipping:

Inventory:144,000
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
NLU2G06CMX1TCG from onsemi is a dual CMOS inverter with open-drain outputs, designed for level-shifting and wired-OR logic in space-constrained applications. It operates from 1.65 V to 5.5 V, delivers 3.8 ns typical propagation delay at 5.0 V, supports ±12.5 mA output sink current, and features overvoltage-tolerant (OVT) inputs/outputs up to 7.0 V - enabling robust interfacing between mixed-voltage domains in industrial I/O and sensor interface circuits.
For engineers reviewing the NLU2G06CMX1TCG datasheet, pinout, applications, or equivalent options, key selection criteria include open-drain flexibility, ultra-small UDFN6 (1.0 × 1.0 mm) packaging, OVT capability across supply ranges, and guaranteed operation from −55 °C to +125 °C for automotive and harsh-environment designs.
Technical Context
The NLU2G06CMX1TCG implements two independent inverting buffers with open-drain outputs, requiring external pull-up resistors for logic high assertion. Its input structure tolerates voltages up to 7.0 V regardless of VCC, decoupling input signal levels from supply rail constraints.
Each inverter exhibits balanced propagation delays (tPZL = tPLZ), supports dynamic switching up to 100 MHz (based on tIN/V = 20 ns/V at 5.0 V), and maintains stable DC electrical behavior across −55 °C to +125 °C with VIH/VIL thresholds scaling linearly with VCC.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.65 V to 5.5 V - enables direct integration into 1.8 V, 2.5 V, 3.3 V, and 5 V systems without level translators. |
| tPD (Typ) | 3.8 ns @ VCC = 5.0 V, CL = 15 pF - supports high-speed digital control signaling in real-time interfaces. |
| IOL (Max) | ±12.5 mA - provides sufficient sink strength for driving LEDs, MOSFET gates, or standard TTL loads. |
| OVT Rating | Inputs/outputs tolerate −0.5 V to +7.0 V - allows safe connection to higher-voltage buses (e.g., 5 V I²C) while powered from lower VCC. |
| Operating Temp | −55 °C to +125 °C - qualified for under-hood automotive, industrial PLC, and outdoor equipment use. |
| Package | UDFN6, 1.0 × 1.0 mm, 0.35 mm pitch - fits high-density PCB layouts where board area is constrained. |
| ICC (Max) | 10 µA @ TA = 25 °C - ensures ultra-low static power in battery-backed or always-on monitoring nodes. |
Pinout & Package
Package: UDFN6 (1.0 × 1.0 mm, 0.35 mm pitch), case 517BX, exposed pad optional, Pb-free, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - IN A1 | Input of first inverter | Accepts logic signals; OVT allows voltage up to 7.0 V independent of VCC. |
| 2 - IN A2 | Input of second inverter | Independent input with identical OVT and threshold behavior as Pin 1. |
| 3 - GND | Ground reference | Primary return path for both inverters and internal ESD structures. |
| 4 - VCC | Positive supply | Supplies core logic; sets VIH/VIL thresholds and determines output high level via external pull-up. |
| 5 - OUT Y2 | Open-drain output of second inverter | Sinks current only; requires external pull-up to define logic high voltage and drive strength. |
| 6 - OUT Y1 | Open-drain output of first inverter | Functionally identical to Pin 5; supports independent wired-OR or level-shifted bus termination. |
Key Features
| Feature | Design Value |
|---|---|
| Overvoltage-tolerant I/O | Enables direct interfacing with 5 V or 7 V buses while operating from 1.8 V supply - eliminates need for discrete level shifters. |
| Ultra-small UDFN6 footprint | 1.0 × 1.0 mm package reduces PCB area by >60% vs. SOIC-8, critical for wearables and compact sensor modules. |
| Power-down input protection | Prevents back-driving and latch-up when VCC = 0 V - supports hot-plug and partial-power-down system architectures. |
| Balanced propagation delays | tPZL ≈ tPLZ ensures symmetrical rise/fall timing in bidirectional bus control and clock inversion paths. |
| Low ICC quiescent current | 10 µA max at 25 °C enables multi-year battery life in IoT endpoint nodes with periodic wake-up events. |
Applications
| Industrial Sensor Interface | Automotive Body Control Module |
|---|---|
|
Use Scenario: Interfacing 5 V analog sensor outputs to a 3.3 V microcontroller ADC input with digital enable control. IC Role / Device Role / Timing Role: Dual inverter acts as level-translated enable gate and fault indicator driver, using open-drain outputs to safely interface mismatched voltage domains. Use Value: Eliminates discrete MOSFET level shifters and reduces BOM count by one active component per channel while maintaining OVT safety margin. |
Use Scenario: Driving LED status indicators and controlling low-side relay drivers in a 12 V vehicle subsystem powered from a 3.3 V LDO. IC Role / Device Role / Timing Role: Provides logic inversion and current-sinking output stage compatible with 12 V pull-ups, leveraging OVT inputs to accept switch inputs referenced to battery voltage. Use Value: Enables single-chip solution for mixed-voltage I/O without external voltage translators or protection diodes. |
| IoT Edge Node Wake-Up Logic | Programmable Logic Controller (PLC) Input Conditioning |
|
Use Scenario: Generating synchronized wake-up pulses from a low-power RTC interrupt to multiple subsystems in a battery-powered environmental monitor. IC Role / Device Role / Timing Role: Inverts and buffers RTC alarm signal; open-drain outputs allow OR-ing of multiple wake sources onto shared interrupt line. Use Value: Supports ultra-low standby current (<1 µA system-level) due to sub-10 µA ICC and power-down protection during sleep mode. |
Use Scenario: Converting 24 V industrial field signals to clean 3.3 V logic levels for FPGA or ARM-based controller inputs. IC Role / Device Role / Timing Role: Serves as front-end signal conditioner - inverts polarity and provides OVT input protection before feeding into digital isolators or MCU GPIOs. Use Value: Withstands transient overvoltages up to 7 V and operates reliably across −40 °C to +85 °C ambient, meeting IEC 61000-4-5 surge immunity requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual open-drain inverter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC2G06DBVR | Same 2-channel open-drain inverter function but rated only to 5.5 V VCC; no OVT - inputs limited to VCC + 0.5 V. | Requires strict voltage alignment; unsuitable for mixed-voltage bus interfacing without external clamping. | Select when operating exclusively within a single 1.65–5.5 V domain and board space permits larger SOT-23-6 (2.9 × 1.6 mm). |
| 74LVC2G06GW,125 | Offers identical OVT capability and 1.65–5.5 V range, but packaged in XSON6 (1.25 × 1.0 mm) - 25% larger footprint than NLU2G06CMX1TCG. | Compatible drop-in replacement for OVT-critical designs where 0.25 mm extra length is acceptable. | Choose when existing layout uses NXP's XSON6 land pattern and full OVT compliance is required. |
Compared with SN74LVC2G06DBVR and 74LVC2G06GW,125, the NLU2G06CMX1TCG uniquely combines true 7.0 V OVT tolerance with the smallest industry-standard UDFN6 footprint (1.0 × 1.0 mm), delivering superior voltage-domain interoperability and PCB area efficiency for next-generation miniaturized electronics.
Availability
NLU2G06CMX1TCG is available at Aetrix Electronics and suitable for industrial sensor interface, automotive body control, IoT edge node wake-up logic, and programmable logic controller (PLC) input conditioning requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for NLU2G06CMX1TCG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier focused on energy-efficient innovation for automotive, industrial, cloud, and intelligent power solutions.
The NLU2G06CMX1TCG belongs to the MiniGate™ family of ultra-small logic devices, engineered specifically for space-constrained, mixed-voltage digital interfacing in automotive and industrial control systems.
FAQ
What is the maximum input voltage the NLU2G06CMX1TCG can tolerate?
The NLU2G06CMX1TCG supports overvoltage-tolerant (OVT) inputs and outputs rated from −0.5 V to +7.0 V, independent of VCC. This means it can safely accept 5 V or even 7 V logic signals while powered from as low as 1.65 V - a key advantage for interfacing legacy or higher-voltage peripherals without external protection components. The NLU2G06CMX1TCG maintains this rating across its full operating temperature range.
Does the NLU2G06CMX1TCG require external pull-up resistors on its outputs?
Yes, the NLU2G06CMX1TCG features open-drain outputs (OUT Y1 and OUT Y2), which can only sink current. To assert a logic HIGH, external pull-up resistors must be connected between each output and a defined voltage rail (e.g., 3.3 V or 5 V). The value of the pull-up resistor determines rise time and power consumption - typical values range from 2.2 kΩ to 10 kΩ depending on speed and load requirements. The NLU2G06CMX1TCG itself does not provide internal pull-ups.
What is the operating temperature range of the NLU2G06CMX1TCG?
The NLU2G06CMX1TCG is specified to operate from −55 °C to +125 °C, making it suitable for under-hood automotive, industrial automation, and outdoor infrastructure applications. This extended range is validated across all DC and AC electrical parameters in the datasheet, including VIH/VIL thresholds, VOL, tPD, and leakage currents. The NLU2G06CMX1TCG maintains functionality and reliability without derating across this full range.
Can the NLU2G06CMX1TCG be used in hot-swap or partial-power-down systems?
Yes, the NLU2G06CMX1TCG includes power-down protection on its inputs, preventing back-current flow and latch-up when VCC = 0 V. This allows safe connection to live buses during insertion or system reconfiguration - a requirement in modular industrial controllers and hot-pluggable sensor nodes. The NLU2G06CMX1TCG remains electrically isolated and non-disruptive to upstream circuitry under zero-supply conditions.
What package type is used for the NLU2G06CMX1TCG?
The NLU2G06CMX1TCG is packaged in a UDFN6 (Ultra-thin Dual Flat No-lead) variant measuring 1.0 mm × 1.0 mm with 0.35 mm pitch and case code 517BX. It features six terminals (two inputs, two outputs, VCC, GND) and an optional exposed thermal pad. This package is Pb-free, RoHS-compliant, and optimized for high-density PCB assembly using standard reflow profiles. The NLU2G06CMX1TCG's footprint is among the smallest in its class, saving significant board area versus SOT-23 or XSON6 alternatives.
NLU2G06CMX1TCG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- MiniGate™
- Package/Case:
- 6-XFLGA
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Logic Type:
- Inverter
- Number of Circuits:
- 2
- Number of Inputs:
- 2
- Features:
- Open Drain
- Voltage - Supply:
- 1.65V ~ 5.5V
- Current - Quiescent (Max):
- 1 µA
- Current - Output High, Low:
- -, 8mA
- Input Logic Level - Low:
- -
- Input Logic Level - High:
- -
- Max Propagation Delay @ V, Max CL:
- 7.5ns @ 5V, 50pF
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-ULLGA (1x1)
NLU2G06CMX1TCG FAQ
1.How can I place an order for NLU2G06CMX1TCG through Aetrix?
Please submit a Request for Quotation (RFQ) for NLU2G06CMX1TCG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NLU2G06CMX1TCG reliable?
The price and inventory of NLU2G06CMX1TCG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NLU2G06CMX1TCG is usually 5 days.
3.What payment methods are accepted for NLU2G06CMX1TCG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NLU2G06CMX1TCG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NLU2G06CMX1TCG?
NLU2G06CMX1TCG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NLU2G06CMX1TCG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NLU2G06CMX1TCG?
For technical support, including NLU2G06CMX1TCG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NLU2G06CMX1TCG requirements.
6.How does Aetrix verify that NLU2G06CMX1TCG is sourced from the original manufacturer or authorized distributors?
All NLU2G06CMX1TCG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NLU2G06CMX1TCG meets industry standards.
7.What is the process for return or replacement of NLU2G06CMX1TCG?
All NLU2G06CMX1TCG units undergo pre-shipment inspection (PSI). If there is an issue with NLU2G06CMX1TCG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NLU2G06CMX1TCG part is unused and in its original packaging.
Return procedure for NLU2G06CMX1TCG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NLU2G06CMX1TCG Tags
-
SN74LVC1G14DBVR
Texas Instruments
-
SN74LVC1G14DCKR
Texas Instruments
-
SN74AHC1G14DBVR
Texas Instruments
-
SN74LVC1G08DBVR
Texas Instruments
-
SN74LVC1G08DCKR
Texas Instruments
-
SN74LVC1G32DCKR
Texas Instruments
-
SN74LVC1G04DBVR
Texas Instruments
.jpg)
-
74LVC1G08GW,125
Nexperia USA Inc.
-
SN74LVC1G04DCKR
Texas Instruments
-
SN74AHC1G08DBVR
Texas Instruments
-
SN74LVC1G32DBVR
Texas Instruments
-
SN74AHCT1G08DBVR
Texas Instruments
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

