onsemi NLV17SZ00DFT2G
- Part No.:
- NLV17SZ00DFT2G
- Manufacturer:
- onsemi
- Category:
- Gates and Inverters
- Package:
- 5-TSSOP, SC-70-5, SOT-353
- Datasheet:
-
NLV17SZ00DFT2G.pdf
- Description:
- IC GATE NAND 1CH 2-INP SC88A
- Quantity:
- Payment:

- Shipping:

Inventory:3,650
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Product details
Overview
NLV17SZ00DFT2G from onsemi is a single 2-input NAND gate logic IC designed for low-voltage, high-speed digital signal conditioning in space-constrained applications. It operates from 1.65 V to 5.5 V, delivers 2.4 ns typical propagation delay at 5 V, supports overvoltage-tolerant inputs/outputs up to 5.5 V, and drives ±24 mA at 3.0 V - enabling direct interface with mixed-voltage systems such as USB peripherals, sensor interface modules, and portable MCU I/O expansion.
For engineers reviewing the NLV17SZ00DFT2G datasheet, pinout, applications, or equivalent options, key selection criteria include supply voltage range compatibility, output drive strength at 3.3 V, input overvoltage tolerance, IOFF partial power-down capability, and SC-88A package footprint constraints for high-density PCB layouts.
Technical Context
The NLV17SZ00DFT2G implements standard CMOS NAND logic using sub-100-FET circuit complexity, with rail-to-rail input voltage acceptance (−0.5 V to VCC + 0.5 V) and active-mode output swing bounded by VOH ≥ VCC − 0.1 V and VOL ≤ 0.42 V at 24 mA sink. Its IOFF feature disables current flow when VCC = 0 V, preventing back-powering of powered-down subsystems.
Propagation delay varies with supply voltage and load: 2.4 ns (typ) at VCC = 5 V with RL = 1 MΩ/CL = 15 pF, degrading to 5.4 ns (typ) at VCC = 1.8 V under identical conditions. Input capacitance is 2.5 pF, and power dissipation capacitance is 9 pF at 3.3 V/10 MHz, supporting low-noise, low-power operation in battery-powered edge nodes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.65 V to 5.5 V - enables interoperability across 1.8 V, 2.5 V, 3.3 V, and 5 V logic domains without level shifters. |
| tPD (Typ) | 2.4 ns at VCC = 5 V, RL = 1 MΩ, CL = 15 pF - supports >200 MHz toggle rates in clean signal paths. |
| IOH/IOL | ±24 mA at VCC = 3.0 V - sufficient to directly drive LEDs, small MOSFET gates, or multiple 74LVC inputs. |
| Input Tolerance | Up to 5.5 V independent of VCC - allows safe interfacing with 5 V signals while operating at 1.8 V supply. |
| IOFF Support | Active when VCC = 0 V - prevents current leakage between powered and unpowered sections in hot-swap or partial-shutdown systems. |
| Operating Temp | −55 °C to +125 °C - qualified for industrial and automotive under-hood environments. |
| Package | SC-88A (Case 419A), 5-pin, 2.1 mm × 1.25 mm footprint - optimized for ultra-compact PCB real estate. |
Pinout & Package
Package: SC-88A (Case 419A), 5-pin surface-mount, 2.1 mm × 1.25 mm × 0.95 mm body, 0.65 mm pitch, Pb-free and RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Input B | Second logic input; accepts −0.5 V to 5.5 V regardless of VCC value. |
| 2 | Input A | Primary logic input; fully overvoltage tolerant and compatible with 5 V TTL levels at 1.65 V operation. |
| 3 | GND | Ground reference for all internal circuitry and output return path. |
| 4 | Output Y | NAND result (Y = NOT(A AND B)); capable of sourcing/sinking 24 mA at 3.0 V with rail-aligned VOH/VOL. |
| 5 | VCC | Positive supply rail; powers internal logic and defines output voltage swing boundaries. |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range (1.65–5.5 V) | Eliminates need for external voltage translators in multi-rail systems like IoT sensor hubs with mixed 1.8 V MCU and 5 V analog front-ends. |
| 2.4 ns tPD at 5 V | Enables use in timing-critical control paths such as reset synchronization, clock gating, or address decoding in microcontroller peripherals. |
| IOFF partial power-down | Prevents back-current injection into VCC during system sleep modes, preserving battery life and avoiding latch-up in always-on subsystems. |
| Overvoltage-tolerant I/O | Allows direct connection to legacy 5 V buses or sensors without external clamping diodes or resistors, reducing BOM count and board area. |
| AEC-Q100 qualified variant available | Supports automotive infotainment and body electronics where reliability under thermal cycling and vibration is mandatory. |
Applications
| USB Device Interface Logic | Sensor Signal Conditioning |
|---|---|
|
Use Scenario: Level translation and signal inversion between a 3.3 V USB controller and 5 V legacy peripheral handshake lines. IC Role / Device Role / Timing Role: NAND gate used as inverter (with one input tied high) to invert USB suspend/resume status signals while maintaining voltage domain isolation. Use Value: Eliminates discrete level shifter ICs; overvoltage tolerance ensures robustness against 5 V transients on handshake lines during plug/unplug events. |
Use Scenario: Debouncing and logic combination of mechanical switch inputs from environmental sensors in industrial monitoring nodes. IC Role / Device Role / Timing Role: Single NAND configured as SR latch to suppress contact bounce, driven by pull-up/pull-down networks on A/B inputs. Use Value: Reduces component count versus RC+Schmitt trigger solutions; 2.4 ns propagation enables sub-microsecond response to fast-switching reed relays. |
| MCU I/O Expansion | Battery-Powered Wearable Control |
|
Use Scenario: Expanding GPIO count on resource-constrained ARM Cortex-M0+ microcontrollers in smart home actuators. IC Role / Device Role / Timing Role: NAND gate used as enable gate for LED driver enable lines, combining MCU output with system-ready flag. Use Value: Enables conditional activation of power stages only when both MCU and power supply are stable, improving system safety and startup sequencing. |
Use Scenario: Power management sequencing in compact wearable devices with dual-voltage PMIC rails (1.8 V core, 3.3 V radio). IC Role / Device Role / Timing Role: NAND gate implements OR logic (via De Morgan) to combine low-battery and shutdown request signals into a unified reset assertion. Use Value: Achieves deterministic shutdown behavior with <100 ns timing skew; IOFF prevents current leakage from 3.3 V radio rail into 1.8 V core domain during deep sleep. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar NAND gate logic applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G00DBVR | Wider VCC range (1.65–5.5 V), same SC-70-5 package, but higher ICC (max 10 µA vs. 1 µA typ for NLV17SZ00DFT2G) and no IOFF support. | Lacks partial power-down protection; unsuitable for systems requiring strict isolation during VCC-off states. | Select when cost sensitivity outweighs IOFF requirement and layout already uses SC-70-5 footprint. |
| 74AUP1G00GW,125 | Lower static current (0.9 µA max), 1.1–3.6 V VCC range only, 3.7 ns tPD at 3.3 V, no overvoltage tolerance beyond VCC. | Not compatible with 5 V signal domains; requires external clamping if interfacing with 5 V sources. | Prefer for ultra-low-power wearables operating strictly at 1.8 V or 3.3 V where 5 V tolerance is unnecessary. |
Compared with SN74LVC1G00DBVR and 74AUP1G00GW,125, the NLV17SZ00DFT2G uniquely combines 5.5 V overvoltage tolerance, IOFF, and SC-88A packaging - making it the only option among the three that safely bridges 1.8 V logic and 5 V legacy interfaces without additional components or layout changes.
Availability
NLV17SZ00DFT2G is available at Aetrix Electronics and suitable for USB interface design, sensor node signal conditioning, MCU I/O expansion, battery-powered wearables, and industrial control logic requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for NLV17SZ00DFT2G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient silicon and SiC solutions for automotive, industrial, cloud, and IoT applications.
The NLV17SZ00DFT2G belongs to onsemi's NLV logic family - engineered for low-voltage, high-reliability operation in harsh environments, with emphasis on overvoltage resilience, partial power-down safety, and AEC-Q100 readiness for automotive-grade deployment.
FAQ
What is the maximum input voltage the NLV17SZ00DFT2G can tolerate when operating at 1.8 V supply?
The NLV17SZ00DFT2G supports input voltages up to 5.5 V regardless of VCC level - meaning it safely accepts 5 V TTL or CMOS signals even when powered at 1.8 V. This eliminates external clamping diodes in mixed-voltage designs and is confirmed in the Absolute Maximum Ratings table (VIN = −0.5 V to +6.5 V) and DC Electrical Characteristics section of the official datasheet.
Does the NLV17SZ00DFT2G support partial power-down (IOFF) functionality, and how does it behave when VCC = 0 V?
Yes, the NLV17SZ00DFT2G features IOFF, which disables current flow through inputs and outputs when VCC = 0 V. Measured IOFF leakage is ≤10 µA per pin under this condition, preventing back-powering of powered-down subsystems. This behavior is explicitly specified in the DC Electrical Characteristics table and is critical for hot-swap and battery-backed system architectures.
What is the typical propagation delay of the NLV17SZ00DFT2G at 3.3 V supply, and under what test conditions is that value measured?
The typical propagation delay (tPLH/tPHL) of the NLV17SZ00DFT2G is 2.7 ns at VCC = 3.3 V, measured with RL = 1 MΩ and CL = 15 pF, per the AC Electrical Characteristics table. This value reflects real-world performance in high-impedance, low-capacitance signal routing - common in FPGA/MCU glue logic and sensor interface paths.
Which package type is used for the NLV17SZ00DFT2G, and what are its key mechanical dimensions?
The NLV17SZ00DFT2G uses the SC-88A (Case 419A) package: a 5-pin, 2.1 mm × 1.25 mm × 0.95 mm surface-mount outline with 0.65 mm lead pitch. Its compact size supports high-density routing in portable electronics, and its pinout (A, B, GND, Y, VCC) is standardized across SC-88A logic devices for layout reuse.
Is the NLV17SZ00DFT2G qualified for automotive applications, and what qualification level does it meet?
The base NLV17SZ00DFT2G is not automotive-qualified, but its −Q suffix variant (NLV17SZ00DFT2G−Q) is AEC-Q100 qualified and PPAP capable. The −Q version undergoes extended temperature stress, ESD, and reliability testing per automotive standards and is marked with unique site/control identifiers - essential for Tier 1 automotive supply chains.
NLV17SZ00DFT2G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 17SZ
- Package/Case:
- 5-TSSOP, SC-70-5, SOT-353
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- NAND Gate
- Number of Circuits:
- 1
- Number of Inputs:
- 2
- Features:
- -
- Voltage - Supply:
- 1.65V ~ 5.5V
- Current - Quiescent (Max):
- 1 µA
- Current - Output High, Low:
- 32mA, 32mA
- Input Logic Level - Low:
- 0.1V ~ 0.55V
- Input Logic Level - High:
- 1.4V ~ 4V
- Max Propagation Delay @ V, Max CL:
- 4.3ns @ 5V, 50pF
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SC-88A (SC-70-5/SOT-353)
NLV17SZ00DFT2G FAQ
1.How can I place an order for NLV17SZ00DFT2G through Aetrix?
Please submit a Request for Quotation (RFQ) for NLV17SZ00DFT2G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NLV17SZ00DFT2G reliable?
The price and inventory of NLV17SZ00DFT2G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NLV17SZ00DFT2G is usually 5 days.
3.What payment methods are accepted for NLV17SZ00DFT2G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NLV17SZ00DFT2G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NLV17SZ00DFT2G?
NLV17SZ00DFT2G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NLV17SZ00DFT2G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NLV17SZ00DFT2G?
For technical support, including NLV17SZ00DFT2G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NLV17SZ00DFT2G requirements.
6.How does Aetrix verify that NLV17SZ00DFT2G is sourced from the original manufacturer or authorized distributors?
All NLV17SZ00DFT2G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NLV17SZ00DFT2G meets industry standards.
7.What is the process for return or replacement of NLV17SZ00DFT2G?
All NLV17SZ00DFT2G units undergo pre-shipment inspection (PSI). If there is an issue with NLV17SZ00DFT2G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NLV17SZ00DFT2G part is unused and in its original packaging.
Return procedure for NLV17SZ00DFT2G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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