onsemi NLV17SZ14DFT2G
- Part No.:
- NLV17SZ14DFT2G
- Manufacturer:
- onsemi
- Category:
- Gates and Inverters
- Package:
- 5-TSSOP, SC-70-5, SOT-353
- Datasheet:
-
NLV17SZ14DFT2G.pdf
- Description:
- IC INVERT SCHMITT 1CH 1INP SC88A
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
NLV17SZ14DFT2G from onsemi is a single Schmitt-trigger inverter IC designed for signal conditioning and noise-immune digital logic inversion in space-constrained applications. It operates from 1.65 V to 5.5 V, delivers 3.7 ns typical propagation delay at 5 V, supports ±24 mA I/O drive at 3.0 V, and features IOFF partial power-down protection - used in industrial sensor interfaces, automotive body control modules, and portable MCU reset circuits.
For engineers reviewing the NLV17SZ14DFT2G datasheet, pinout, applications, or equivalent options, key selection criteria include its 5-pin SC-88A package, Schmitt-trigger hysteresis (0.48 V typ at 1.65 V), input overvoltage tolerance up to 5.5 V, and AEC-Q100 qualification for automotive use cases requiring robust noise immunity and rail-to-rail compatibility.
Technical Context
The NLV17SZ14DFT2G implements a single CMOS inverter with Schmitt-trigger input thresholds (VT+ = 1.4 V, VT− = 0.5 V at 1.65 V) to reject analog noise on slow or noisy digital signals. Its IOFF circuitry disables I/O leakage when VCC = 0 V, enabling live insertion and hot-swap capability in multi-rail systems.
It supports rail-to-rail operation across 1.65–5.5 V supply range, maintains consistent hysteresis (0.48–1.7 V) and propagation delay (3.1–15.6 ns) across voltage and temperature (−55 °C to +125 °C), and exhibits low input capacitance (2.5 pF) and power dissipation capacitance (9–11 pF) for high-speed, low-power interfacing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.65 V to 5.5 V - enables direct interface with 1.8 V, 2.5 V, 3.3 V, and 5 V logic families without level shifters. |
| tPD (typ) | 3.7 ns at VCC = 5 V, RL = 1 MΩ, CL = 15 pF - ensures fast signal inversion for timing-critical edge detection. |
| IOFF Support | Active power-down isolation - prevents back-driving and leakage when VCC is unpowered, critical for system-level hot-swap compliance. |
| Input Hysteresis | 0.48 V (min) at 1.65 V - rejects >480 mV of noise on input transitions, eliminating false triggering in EMI-prone environments. |
| I/O Drive | ±24 mA at VCC = 3.0 V - directly drives LEDs, small relays, or multiple standard-load CMOS inputs without external buffers. |
| ESD Rating | HBM 2000 V, CDM 1000 V - meets industrial and automotive board-level ESD robustness requirements per JEDEC standards. |
| Operating Temp | −55 °C to +125 °C - qualified for under-hood automotive, industrial control, and extended-temperature embedded applications. |
Pinout & Package
Package: SC-88A (Case 419A), 5-pin surface-mount, 2.1 mm × 1.25 mm × 0.95 mm footprint with 0.65 mm pitch - optimized for high-density PCB layouts in compact consumer and automotive modules.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | No-connect (NC) | Internally unconnected - must be left floating or tied to GND per layout best practice; no electrical function. |
| 2 | Input (A) | Schmitt-trigger input - accepts 0–5.5 V logic signals regardless of VCC; immune to slow edges and noise. |
| 3 | GND | Ground reference - provides return path for all internal logic and I/O current; requires low-impedance PCB connection. |
| 4 | Output (Y) | Inverted Schmitt output - actively driven high/low with rail-to-rail swing and 24 mA sink/source capability at 3 V. |
| 5 | VCC | Positive supply - powers internal logic; supports IOFF behavior when de-energized; decoupling capacitor required. |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger input | Provides 0.48–1.7 V hysteresis to eliminate chatter on slow or noisy signals - essential for switch debouncing and analog sensor digitization. |
| IOFF partial power-down | Blocks I/O leakage (<1.0 µA) when VCC = 0 V - enables safe hot-plug operation and prevents bus contention in multi-supply systems. |
| Rail-to-rail I/O tolerance | Accepts and outputs up to 5.5 V independent of VCC - simplifies interfacing with mixed-voltage peripherals and legacy 5 V sensors. |
| Low dynamic power | CPD = 9–11 pF - minimizes switching current (ICC(OPR) = CPD × VCC² × f + ICC), reducing heat and supply ripple at 10 MHz operation. |
| AEC-Q100 qualified | Qualified to Grade 1 (−40 °C to +125 °C) and PPAP-capable - meets automotive electronics reliability and traceability requirements. |
Applications
| Industrial Sensor Interface | Automotive Body Control |
|---|---|
|
Use Scenario: Converting noisy analog sensor outputs (e.g., thermistor, potentiometer) into clean digital logic levels for MCU ADC trigger or comparator input. IC Role / Device Role / Timing Role: Signal conditioner and noise-immune inverter - converts slow-rising/falling analog edges into sharp, jitter-free digital transitions. Use Value: Eliminates need for external RC filtering or op-amp comparators; reduces BOM count and PCB area while improving long-term stability against EMI. |
Use Scenario: Debouncing mechanical switches in door lock actuators, mirror controls, or lighting modules within automotive body ECUs. IC Role / Device Role / Timing Role: Digital input conditioner - suppresses contact bounce and conducted noise before reaching safety-critical microcontroller GPIOs. Use Value: Ensures deterministic switch state capture without firmware polling delays; meets ISO 11452-4 immunity requirements via hardware-level noise rejection. |
| Portable MCU Reset Circuit | Legacy 5 V Logic Level Translation |
|
Use Scenario: Generating clean, glitch-free reset pulses for low-power microcontrollers in battery-operated IoT nodes using push-button or watchdog inputs. IC Role / Device Role / Timing Role: Edge-shaping inverter - converts manual button press (slow rise/fall) into precise reset assertion/deassertion timing. Use Value: Guarantees minimum reset pulse width and eliminates false resets due to mechanical vibration or ESD transients - improves field reliability. |
Use Scenario: Interfacing modern 3.3 V MCUs with legacy 5 V peripherals (e.g., displays, EEPROMs) where bidirectional translation isn't needed. IC Role / Device Role / Timing Role: Unidirectional level translator - accepts 5 V input while powered from 3.3 V, outputs full 3.3 V logic swing. Use Value: Avoids dedicated level translators; leverages input overvoltage tolerance and rail-to-rail output to simplify voltage domain bridging. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Schmitt-trigger inverter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MC74VHC1GT14DTT1G | Same SC-88A package, 2.0–5.5 V VCC range, 3.5 ns tPD at 5 V, but lacks IOFF and AEC-Q100 qualification. | Not suitable for hot-swap or automotive applications requiring power-down isolation or PPAP documentation. | Select when cost sensitivity outweighs automotive qualification and IOFF requirement; verify system-level power sequencing. |
| SN74LVC1G14DBVR | SC-74A package (larger than SC-88A), 1.65–5.5 V, 4.5 ns tPD at 3.3 V, IOFF supported, but not AEC-Q100 qualified. | Acceptable for industrial use but requires rework for automotive deployment due to missing qualification and different footprint. | Choose if SC-74A is already standardized in design; confirm thermal derating (JA = 320 °C/W vs. NLV17SZ14DFT2G's 377 °C/W). |
Compared with MC74VHC1GT14DTT1G and SN74LVC1G14DBVR, the NLV17SZ14DFT2G uniquely combines AEC-Q100 qualification, IOFF, and SC-88A packaging - making it the only drop-in solution for space-constrained automotive modules requiring both hot-swap safety and production traceability.
Availability
NLV17SZ14DFT2G is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive body control units, and portable MCU reset circuits requiring stable component supply, long-term lifecycle support, and automotive-grade traceability.
Supply support for NLV17SZ14DFT2G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi is a global semiconductor supplier delivering energy-efficient, intelligent power and sensing solutions for automotive, industrial, cloud, medical, and IoT applications.
The NLV17SZ14DFT2G belongs to onsemi's TinyLogic® family of ultra-small logic ICs - engineered specifically for space-constrained, noise-sensitive digital signal conditioning in automotive and industrial edge devices.
FAQ
What is the pin configuration of the NLV17SZ14DFT2G?
The NLV17SZ14DFT2G uses a 5-pin SC-88A package with pinout: Pin 1 = NC, Pin 2 = Input (A), Pin 3 = GND, Pin 4 = Output (Y), Pin 5 = VCC. This configuration is confirmed in Figure 2 and the PIN ASSIGNMENT table of the official datasheet (Rev. 20, January 2026). Pin 1 is internally unconnected and must remain floating or grounded per layout guidelines.
Does the NLV17SZ14DFT2G support partial power-down functionality?
Yes, the NLV17SZ14DFT2G supports IOFF partial power-down protection. When VCC = 0 V, the input and output ports enter a high-impedance state with leakage current limited to ≤10 µA (max), preventing back-driving and bus contention. This feature is explicitly specified in the datasheet Features section and DC Electrical Characteristics table under IOFF parameter.
Is the NLV17SZ14DFT2G qualified for automotive applications?
Yes, the NLV17SZ14DFT2G is AEC-Q100 qualified and PPAP capable. The "−Q" suffix variant (NLV17SZ14DFT2G-Q) is explicitly designated for automotive use, and the base part shares the same qualification. It meets Grade 1 temperature range (−40 °C to +125 °C), ESD (HBM 2000 V), and latch-up (100 mA) requirements defined in the datasheet's Maximum Ratings and Features sections.
What is the typical propagation delay of the NLV17SZ14DFT2G at 3.3 V?
The typical propagation delay (tPLH/tPHL) of the NLV17SZ14DFT2G is 4.4 ns at VCC = 3.3 V, RL = 500 Ω, and CL = 50 pF, as specified in the AC Electrical Characteristics table (page 5). At 3.0 V with RL = 1 MΩ and CL = 15 pF, it is 3.7 ns (typ). These values are measured under defined load conditions and vary with voltage, temperature, and capacitive loading.
Can the NLV17SZ14DFT2G accept 5 V input signals while operating from a 3.3 V supply?
Yes, the NLV17SZ14DFT2G supports input overvoltage tolerance up to 5.5 V regardless of VCC level - meaning it can safely accept 5 V logic inputs while powered from 1.65–5.5 V, including 3.3 V. This is confirmed in the Features list and DC Electrical Characteristics table under VIN specification (0 to 5.5 V), enabling direct interfacing with legacy 5 V peripherals.
NLV17SZ14DFT2G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 17SZ
- Package/Case:
- 5-TSSOP, SC-70-5, SOT-353
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Inverter
- Number of Circuits:
- 1
- Number of Inputs:
- 1
- Features:
- Schmitt Trigger
- Voltage - Supply:
- 1.65V ~ 5.5V
- Current - Quiescent (Max):
- 1 µA
- Current - Output High, Low:
- 32mA, 32mA
- Input Logic Level - Low:
- 0.2V ~ 1.2V
- Input Logic Level - High:
- 1.4V ~ 3.6V
- Max Propagation Delay @ V, Max CL:
- 5.9ns @ 5V, 50pF
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SC-88A (SC-70-5/SOT-353)
NLV17SZ14DFT2G FAQ
1.How can I place an order for NLV17SZ14DFT2G through Aetrix?
Please submit a Request for Quotation (RFQ) for NLV17SZ14DFT2G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NLV17SZ14DFT2G reliable?
The price and inventory of NLV17SZ14DFT2G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NLV17SZ14DFT2G is usually 5 days.
3.What payment methods are accepted for NLV17SZ14DFT2G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NLV17SZ14DFT2G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NLV17SZ14DFT2G?
NLV17SZ14DFT2G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NLV17SZ14DFT2G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NLV17SZ14DFT2G?
For technical support, including NLV17SZ14DFT2G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NLV17SZ14DFT2G requirements.
6.How does Aetrix verify that NLV17SZ14DFT2G is sourced from the original manufacturer or authorized distributors?
All NLV17SZ14DFT2G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NLV17SZ14DFT2G meets industry standards.
7.What is the process for return or replacement of NLV17SZ14DFT2G?
All NLV17SZ14DFT2G units undergo pre-shipment inspection (PSI). If there is an issue with NLV17SZ14DFT2G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NLV17SZ14DFT2G part is unused and in its original packaging.
Return procedure for NLV17SZ14DFT2G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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