onsemi NLV18SZ32DFT2G
- Part No.:
- NLV18SZ32DFT2G
- Manufacturer:
- onsemi
- Category:
- Gates and Inverters
- Package:
- 5-TSSOP, SC-70-5, SOT-353
- Datasheet:
-
NLV18SZ32DFT2G.pdf
- Description:
- IC GATE OR SCHMITT 1CH 2IN SC88A
- Quantity:
- Payment:

- Shipping:

Inventory:1,725
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
NLV18SZ32DFT2G from onsemi is an automotive-grade 2-input OR gate logic IC in SC-88A (SOT-353) package, operating from 1.65 V to 5.5 V, with typical propagation delay of 3.7 ns at VCC = 3.0 V and ±24 mA output drive capability. It supports AEC-Q100 Grade 1 (−40°C to +125°C) and is used in vehicle body control modules for discrete signal combining and level-sensitive decision logic.
For engineers reviewing the NLV18SZ32DFT2G datasheet, pinout, applications, or equivalent options, key selection criteria include its guaranteed operation across automotive temperature range, balanced tPLH/tPHL, symmetrical IOH/IOL, low input leakage (<±0.1 µA), and SC-88A footprint compatibility with space-constrained ECUs.
Technical Context
The NLV18SZ32DFT2G implements a single 2-input CMOS OR gate with rail-to-rail output swing and internally matched P/N channel drive strength. Its input threshold voltages (VT+ = 1.9 V, VT− = 0.6 V at VCC = 3.0 V) and hysteresis (0.4 V typical) provide robust noise immunity in noisy automotive environments.
It features balanced propagation delays (tPLH = tPHL = 3.7 ns typ at VCC = 3.0 V, CL = 15 pF), symmetrical output impedance (IOH = IOL = 24 mA @ VCC = 3.0 V), and operates within −55°C to +125°C ambient range-AEC-Q100 qualified for Grade 1 applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.65 V to 5.5 V - supports wide-input-voltage microcontroller interfaces and legacy 5 V systems |
| tPD (Typ) | 3.7 ns at VCC = 3.0 V, CL = 15 pF - enables high-speed signal routing in real-time control paths |
| IOH/IOL | ±24 mA @ VCC = 3.0 V - drives multiple CMOS inputs or small LEDs without external buffers |
| Operating Temp | −55°C to +125°C - meets full automotive under-hood thermal requirements |
| Input Leakage | ±0.1 µA max @ TA = 25°C - minimizes standby current in always-on domains |
| ESD Rating | HBM: 2000 V - withstands handling and board-level ESD events per AEC-Q100 |
Pinout & Package
SC-88A (SOT-353) 5-pin surface-mount package: 2.2 mm × 1.35 mm × 0.95 mm body, 0.65 mm pitch, Pb-free and RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | B (Input) | Second OR gate input; accepts 0–5.5 V logic levels independent of VCC |
| 2 | A (Input) | Primary OR gate input; TTL- and CMOS-compatible thresholds |
| 3 | GND | Dedicated ground reference; must be low-inductance connection for noise immunity |
| 4 | Y (Output) | Push-pull CMOS output; rail-to-rail swing, capable of sourcing/sinking 24 mA |
| 5 | VCC | Single positive supply; decoupling capacitor required within 1 cm for stable high-speed operation |
Key Features
| Feature | Design Value |
|---|---|
| High-Speed OR Logic | 3.7 ns typical propagation delay enables sub-10 ns decision timing in safety-critical control loops |
| AEC-Q100 Grade 1 Qualified | Validated for −40°C to +125°C operation with PPAP documentation support for automotive OEMs |
| Symmetrical Output Drive | IOH = IOL = 24 mA ensures consistent rise/fall times and minimal duty-cycle distortion |
| Low Input Leakage | ±0.1 µA max reduces parasitic loading on upstream sensors or resistive-divider networks |
| Wide Supply Range | 1.65–5.5 V operation allows direct interface with 1.8 V, 2.5 V, 3.3 V, and 5 V subsystems |
Applications
| Body Control Module (BCM) | Powertrain Sensor Interface |
|---|---|
Use Scenario: Combining door-open and trunk-open signals to trigger interior lighting activation. IC Role / Device Role / Timing Role: Single 2-input OR gate performing real-time logical OR of two independent switch inputs. Use Value: Eliminates need for microcontroller GPIO polling; provides deterministic <4 ns response with no firmware latency. | Use Scenario: Merging camshaft and crankshaft position fault flags before sending to engine ECU. IC Role / Device Role / Timing Role: Fault-aggregation node that asserts "engine sync error" if either sensor reports invalid status. Use Value: Enables hardware-level fail-safe detection with guaranteed timing-no software dependency or interrupt latency. |
| ADAS Camera Power Sequencing | Infotainment System Wake-Up Logic |
Use Scenario: OR-ing power-good signals from image sensor and ISP to enable camera module power rail. IC Role / Device Role / Timing Role: Power-enable combiner ensuring camera powers up only when both subsystems are ready. Use Value: Prevents partial initialization and lockup by enforcing strict dual-rail readiness before enabling downstream regulators. | Use Scenario: Aggregating wake requests from Bluetooth, USB, and CAN bus to exit low-power sleep mode. IC Role / Device Role / Timing Role: Low-leakage OR gate acting as hardware wake-source merger for SoC PMIC control. Use Value: Reduces system standby current by >1 µA vs. MCU-based polling while maintaining sub-microsecond wake latency. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 2-input OR gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MC74VHC1G32DTT1G | Same SC-88A package, but rated only to +105°C (non-AEC); tPD = 3.5 ns typ at VCC = 3.3 V | Not AEC-Q100 qualified; unsuitable for under-hood or safety-critical use | Select only for non-automotive industrial or consumer designs requiring identical footprint and speed |
| SN74LVC1G32DBVR | SC-70-5 package (same pinout), wider VCC range (1.65–5.5 V), but only rated to +85°C industrial temp | Lacks automotive qualification and extended temperature validation; lower ESD rating (HBM = 2 kV vs. 2 kV, but no CDM spec) | Use where cost is primary constraint and AEC-Q100 compliance is not required |
Compared with MC74VHC1G32DTT1G and SN74LVC1G32DBVR, the NLV18SZ32DFT2G uniquely delivers AEC-Q100 Grade 1 qualification, −55°C to +125°C operation, and production traceability required for automotive Tier 1 BOMs-without compromising speed or drive strength.
Availability
NLV18SZ32DFT2G is available at Aetrix Electronics and suitable for automotive body electronics, powertrain diagnostics, ADAS sensor fusion, and infotainment wake-up logic requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for NLV18SZ32DFT2G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier focused on energy-efficient electronics for automotive, industrial, cloud, medical, and IoT applications.
The NLV18SZxx family was designed specifically for automotive signal conditioning and discrete logic functions in harsh-environment ECUs-emphasizing AEC-Q100 compliance, wide temperature operation, and high noise immunity.
FAQ
What is the maximum operating temperature for NLV18SZ32DFT2G?
The NLV18SZ32DFT2G is specified for operation from −55°C to +125°C ambient temperature and is AEC-Q100 Grade 1 qualified (−40°C to +125°C). This makes it suitable for under-hood automotive applications where sustained high-temperature exposure occurs, and its thermal resistance (θJA = 659°C/W) is validated for SC-88A mounting on standard FR4 PCBs.
Does NLV18SZ32DFT2G support 1.8 V logic systems?
Yes, NLV18SZ32DFT2G supports 1.8 V logic systems: its minimum VCC is 1.65 V, and input thresholds scale with supply (VIH = 0.65×VCC, VIL = 0.35×VCC). At VCC = 1.8 V, it guarantees correct switching with VIH ≥ 1.17 V and VIL ≤ 0.63 V, matching standard 1.8 V CMOS interface levels.
Is NLV18SZ32DFT2G pin-compatible with other SC-88A logic gates?
Yes, NLV18SZ32DFT2G uses the standard SC-88A (SOT-353) 5-pin pinout shared across the NLV18SZxx family: Pin 1 = B, Pin 2 = A, Pin 3 = GND, Pin 4 = Y, Pin 5 = VCC. This allows direct substitution with other NLV18SZxx gates (e.g., NLV18SZ04DFT2G, NLV18SZ08DFT2G) without PCB changes-provided function and timing requirements align.
What is the output drive capability of NLV18SZ32DFT2G at 3.3 V supply?
At VCC = 3.3 V, NLV18SZ32DFT2G delivers IOH = −24 mA (source) and IOL = 24 mA (sink) while maintaining VOH ≥ 2.7 V and VOL ≤ 0.4 V. This drive strength supports fan-out of ≥10 74LVC inputs or direct LED driving (with series resistor), verified across −40°C to +125°C per AEC-Q100 test conditions.
Can NLV18SZ32DFT2G be used in battery-powered automotive modules?
Yes, NLV18SZ32DFT2G is well-suited for battery-powered automotive modules: its quiescent ICC is ≤1.0 µA at VCC = 5.5 V and TA = 25°C, and input leakage remains ≤±1.0 µA over full temperature range. Combined with its 1.65 V minimum supply, it enables ultra-low-power wake-up logic in always-on domains such as telematics or remote keyless entry receivers.
NLV18SZ32DFT2G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 18SZ
- Package/Case:
- 5-TSSOP, SC-70-5, SOT-353
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- OR Gate
- Number of Circuits:
- 1
- Number of Inputs:
- 2
- Features:
- -
- Voltage - Supply:
- 1.65V ~ 5.5V
- Current - Quiescent (Max):
- 1 µA
- Current - Output High, Low:
- 32mA, 32mA
- Input Logic Level - Low:
- 0.5V ~ 1.9V
- Input Logic Level - High:
- 1.4V ~ 3.6V
- Max Propagation Delay @ V, Max CL:
- 5.9ns @ 5V, 50pF
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SC-88A (SC-70-5/SOT-353)
NLV18SZ32DFT2G FAQ
1.How can I place an order for NLV18SZ32DFT2G through Aetrix?
Please submit a Request for Quotation (RFQ) for NLV18SZ32DFT2G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NLV18SZ32DFT2G reliable?
The price and inventory of NLV18SZ32DFT2G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NLV18SZ32DFT2G is usually 5 days.
3.What payment methods are accepted for NLV18SZ32DFT2G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NLV18SZ32DFT2G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NLV18SZ32DFT2G?
NLV18SZ32DFT2G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NLV18SZ32DFT2G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NLV18SZ32DFT2G?
For technical support, including NLV18SZ32DFT2G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NLV18SZ32DFT2G requirements.
6.How does Aetrix verify that NLV18SZ32DFT2G is sourced from the original manufacturer or authorized distributors?
All NLV18SZ32DFT2G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NLV18SZ32DFT2G meets industry standards.
7.What is the process for return or replacement of NLV18SZ32DFT2G?
All NLV18SZ32DFT2G units undergo pre-shipment inspection (PSI). If there is an issue with NLV18SZ32DFT2G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NLV18SZ32DFT2G part is unused and in its original packaging.
Return procedure for NLV18SZ32DFT2G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NLV18SZ32DFT2G Tags
-
SN74LVC1G14DBVR
Texas Instruments
-
SN74LVC1G14DCKR
Texas Instruments
-
SN74AHC1G14DBVR
Texas Instruments
-
SN74LVC1G08DBVR
Texas Instruments
-
SN74LVC1G08DCKR
Texas Instruments
-
SN74LVC1G32DCKR
Texas Instruments
-
SN74LVC1G04DBVR
Texas Instruments
.jpg)
-
74LVC1G08GW,125
Nexperia USA Inc.
-
SN74LVC1G04DCKR
Texas Instruments
-
SN74AHC1G08DBVR
Texas Instruments
-
SN74LVC1G32DBVR
Texas Instruments
-
SN74AHCT1G08DBVR
Texas Instruments
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

