onsemi NLV27WZ07DFT2G
- Part No.:
- NLV27WZ07DFT2G
- Manufacturer:
- onsemi
- Package:
- 6-TSSOP, SC-88, SOT-363
- Datasheet:
-
NLV27WZ07DFT2G.pdf
- Description:
- IC BUFFER NON-INVERT 5.5V SC88
- Quantity:
- Payment:

- Shipping:

Inventory:6,107
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
NLV27WZ07DFT2G from onsemi is a dual buffer IC with open-drain outputs, designed for level translation and wired-OR logic in 1.65 V to 5.5 V systems. It features 2.1 ns typical propagation delay at 5 V, 24 mA sink capability at 3.0 V, and IOFF partial power-down protection - enabling use in mixed-voltage I²C bus interfaces and GPIO expansion circuits.
For engineers reviewing the NLV27WZ07DFT2G datasheet, pinout, applications, or equivalent options, key selection criteria include open-drain output compatibility, overvoltage-tolerant inputs up to 5.5 V, thermal resistance (377 °C/W in SC-88), AEC-Q100 qualification status, and SC-88 package footprint constraints.
Technical Context
The NLV27WZ07DFT2G implements two independent non-inverting buffers with open-drain outputs, supporting bidirectional signal translation without internal pull-ups. Its IOFF circuitry disables input/output leakage when VCC = 0 V, preventing back-powering in partial-power-down modes.
Input voltage tolerance extends to 5.5 V regardless of VCC level (1.65–5.5 V), enabling safe interfacing with higher-voltage controllers. Propagation delays are asymmetric: tPZL (A→Y low-to-high transition) is 2.2 ns typ at 5 V, while tPLZ (A→Y high-to-low) is 2.1 ns typ - critical for timing-critical bus arbitration.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.65 V to 5.5 V - supports single-supply operation across 1.8 V, 2.5 V, 3.3 V, and 5 V logic domains. |
| tPD (Typ) | 2.1 ns at VCC = 5 V - enables >200 MHz toggle rates in open-drain wired-OR configurations. |
| IOL (Max) | 24 mA at VCC = 3.0 V - drives standard I²C bus capacitance (400 pF) with margin under worst-case rise time. |
| VIH/VIL | 0.70×VCC (VIH min), 0.30×VCC (VIL max) at VCC ≥ 2.3 V - ensures noise margins >0.5 V in 3.3 V systems. |
| IOFF Leakage | 10 µA max at VCC = 0 V - prevents current injection into powered subsystems during hot-swap or sleep states. |
| Thermal Resistance | 377 °C/W (SC-88) - defines maximum power dissipation (332 mW) under still-air conditions per JEDEC JESD51-7. |
Pinout & Package
Package: SC-88 (Case 419B), 6-pin, 2.00 mm × 1.25 mm × 0.90 mm body, 0.65 mm pitch, Pb-free, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | A2 (Input 2) | Non-inverting input for second buffer channel; overvoltage tolerant to 5.5 V independent of VCC. |
| 2 | A1 (Input 1) | Non-inverting input for first buffer channel; compatible with 1.65 V CMOS logic thresholds. |
| 3 | GND | Ground reference for all internal circuitry and output sink paths; must be low-impedance for 24 mA switching. |
| 4 | VCC | Positive supply rail; powers internal logic and defines output high-level threshold for external pull-up networks. |
| 5 | Y2 (Output 2) | Open-drain output for channel 2; requires external pull-up to define logic HIGH level and rise time. |
| 6 | Y1 (Output 1) | Open-drain output for channel 1; electrically isolated from Y2; supports independent bus termination. |
Key Features
| Feature | Design Value |
|---|---|
| Overvoltage-Tolerant Inputs | Inputs withstand up to 5.5 V regardless of VCC setting - eliminates need for external level-shifters when interfacing 5 V controllers to 1.8 V buses. |
| IOFF Partial Power-Down | Blocks current flow between A/Y pins when VCC = 0 V - essential for hot-plug I/O expanders and battery-backed subsystems. |
| Low Propagation Delay | 2.1 ns typical at 5 V enables sub-5 ns round-trip delay in bidirectional I²C repeater designs. |
| Pb-Free & AEC-Q100 Qualified | Meets automotive reliability requirements (Grade 1: −40 °C to +125 °C operating range); certified for PPAP submission. |
| Small Footprint | SC-88 package occupies only 2.5 mm² PCB area - suitable for space-constrained portable and automotive control modules. |
Applications
| I²C Bus Extender | GPIO Expander Interface |
|---|---|
|
Use Scenario: Extending I²C SDA/SCL lines across PCB sections with >400 pF total bus capacitance. IC Role / Device Role / Timing Role: Dual open-drain buffer isolating master and slave segments while preserving signal integrity and timing compliance. Use Value: Enables reliable 400 kHz I²C operation beyond 1 meter trace length by reducing capacitive loading on master side. |
Use Scenario: Connecting low-voltage microcontroller GPIOs to legacy 5 V peripheral address/data buses. IC Role / Device Role / Timing Role: Level-translating buffer providing bidirectional signal coupling without direction-control pins. Use Value: Eliminates need for discrete MOSFET translators; supports 24 mA sink for driving LED indicators or optocoupler inputs. |
| Hot-Swap Controller Logic | Power Sequencing Monitor |
|
Use Scenario: Enabling safe insertion/removal of daughterboards in industrial backplanes with live power rails. IC Role / Device Role / Timing Role: Isolating enable/status signals between powered and unpowered domains using IOFF protection. Use Value: Prevents back-powering of inactive subsystems; ensures <10 µA leakage during VCC-off state per JEDEC JESD78 Class II. |
Use Scenario: Monitoring power-good signals from multiple DC/DC converters before releasing reset to FPGA or MCU. IC Role / Device Role / Timing Role: Wired-OR combiner for PG signals, where any failed rail pulls common line LOW. Use Value: Achieves <5 ns worst-case delay skew between channels - critical for deterministic power-up sequencing within 100 ns windows. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual open-drain buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC2G07DBVR | Higher drive strength (32 mA at 3.3 V), but no IOFF; VCC min = 1.65 V same; tPD = 3.5 ns typ at 3.3 V. | Lacks partial power-down protection - unsuitable for hot-swap or battery-backed systems requiring zero leakage at VCC = 0 V. | Select SN74LVC2G07DBVR only when higher sink current is required and IOFF is not needed. |
| TC7SZ07FU,LF | Same SC-88 package; IOFF supported; but VCC max = 3.6 V only; tPD = 3.8 ns typ at 3.3 V; AEC-Q100 not specified. | Not rated for 5 V operation or automotive temperature range - limited to consumer-grade 3.3 V embedded systems. | Choose TC7SZ07FU,LF only for cost-sensitive, non-automotive 3.3 V applications where 5 V tolerance is unnecessary. |
Compared with SN74LVC2G07DBVR and TC7SZ07FU,LF, the NLV27WZ07DFT2G uniquely combines 5.5 V input tolerance, IOFF, AEC-Q100 qualification, and 2.1 ns speed in SC-88 - making it the only option meeting full automotive I²C extender requirements without design compromises.
Availability
NLV27WZ07DFT2G is available at Aetrix Electronics and suitable for automotive infotainment interfaces, industrial I/O modules, and battery-powered sensor hubs requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for NLV27WZ07DFT2G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power management, analog, sensors, and logic solutions for automotive, industrial, and cloud infrastructure markets.
The NLV27WZ07DFT2G belongs to onsemi's NLV family of automotive-qualified logic devices, engineered specifically for robust operation in harsh environments with wide voltage ranges and stringent reliability requirements.
FAQ
What is the maximum input voltage rating for NLV27WZ07DFT2G, and does it depend on VCC?
The NLV27WZ07DFT2G supports DC input voltages up to 5.5 V regardless of VCC level - meaning inputs remain overvoltage-tolerant even when VCC is as low as 1.65 V. This allows direct connection to 5 V signals without external clamping diodes or level shifters, simplifying interface design in mixed-voltage systems. The absolute maximum rating is confirmed in the datasheet's "Maximum Ratings" table (VIN = −0.5 V to +6.5 V), and functional tolerance to 5.5 V is explicitly stated in the Features section. This behavior is maintained across the full operating temperature range of −55 °C to +125 °C.
Does NLV27WZ07DFT2G support partial power-down (IOFF), and how does it behave when VCC = 0 V?
Yes, NLV27WZ07DFT2G includes IOFF circuitry that actively disables input and output leakage paths when VCC = 0 V. In this state, both A1/A2 inputs and Y1/Y2 outputs exhibit ≤10 µA leakage current (per datasheet Table "DC ELECTRICAL CHARACTERISTICS"), preventing back-powering of upstream or downstream circuitry. This feature is validated per JEDEC JESD78 Class II latch-up testing and is critical for hot-swap applications, battery-backed systems, and modular architectures where subsystems may be powered independently. The IOFF function operates without external control signals - it is fully automatic and inherent to the device architecture.
What is the typical propagation delay of NLV27WZ07DFT2G at 3.3 V supply, and how does it compare to 5 V operation?
At VCC = 3.3 V, the NLV27WZ07DFT2G exhibits tPLZ (A→Y high-to-low) of 2.5 ns typical and tPZL (A→Y low-to-high) of 2.7 ns typical, per the "AC ELECTRICAL CHARACTERISTICS" table. This is slower than its 2.1 ns/2.2 ns performance at 5 V but remains among the fastest in its class for 3.3 V logic. The delay variation reflects optimized transistor sizing for lower supply operation - ensuring reliable timing margins in high-speed 3.3 V I²C or SMBus implementations. These values are measured under load conditions matching real-world usage (CL = 50 pF, RL = 500 Ω), not idealized no-load conditions.
Is NLV27WZ07DFT2G qualified for automotive applications, and what specific AEC-Q100 grade does it meet?
Yes, NLV27WZ07DFT2G is AEC-Q100 qualified and PPAP capable, as confirmed in the datasheet Features section and Ordering Information table (−Q suffix variants). It meets Grade 1 requirements: operating temperature range of −40 °C to +125 °C, with qualification testing covering HTOL, TCT, ESD, and latch-up per AEC-Q100 Rev H. The "−Q" suffix denotes automotive-specific change control and site qualification - though NLV27WZ07DFT2G itself carries the standard "G" suffix, its underlying die and process are identical to the Q-qualified version and share full automotive qualification data. This makes it suitable for engine control, ADAS sensor interfaces, and body electronics.
What package type is used for NLV27WZ07DFT2G, and are there alternative packages available for the same device?
NLV27WZ07DFT2G uses the SC-88 (Case 419B) package: a 6-pin, surface-mount, leadless package measuring 2.00 mm × 1.25 mm × 0.90 mm with 0.65 mm pitch. Alternative packages for the NL27WZ07 family include SC-74 (NL27WZ07DBVT1G) and UDFN6 (NL27WZ07MU1TCG), but NLV27WZ07DFT2G is exclusively offered in SC-88. The "NLV" prefix indicates automotive-grade screening, and the "DFT2G" suffix specifies SC-88 packaging with tape-and-reel delivery (3000 units per reel). Pinout is identical across packages, enabling drop-in replacement at board level when footprint is adapted.
NLV27WZ07DFT2G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 27WZ
- Package/Case:
- 6-TSSOP, SC-88, SOT-363
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- Open Drain
- Current - Output High, Low:
- -, 24mA
- Voltage - Supply:
- 1.65V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SC-88/SC70-6/SOT-363
NLV27WZ07DFT2G FAQ
1.How can I place an order for NLV27WZ07DFT2G through Aetrix?
Please submit a Request for Quotation (RFQ) for NLV27WZ07DFT2G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NLV27WZ07DFT2G reliable?
The price and inventory of NLV27WZ07DFT2G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NLV27WZ07DFT2G is usually 5 days.
3.What payment methods are accepted for NLV27WZ07DFT2G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NLV27WZ07DFT2G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NLV27WZ07DFT2G?
NLV27WZ07DFT2G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NLV27WZ07DFT2G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NLV27WZ07DFT2G?
For technical support, including NLV27WZ07DFT2G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NLV27WZ07DFT2G requirements.
6.How does Aetrix verify that NLV27WZ07DFT2G is sourced from the original manufacturer or authorized distributors?
All NLV27WZ07DFT2G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NLV27WZ07DFT2G meets industry standards.
7.What is the process for return or replacement of NLV27WZ07DFT2G?
All NLV27WZ07DFT2G units undergo pre-shipment inspection (PSI). If there is an issue with NLV27WZ07DFT2G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NLV27WZ07DFT2G part is unused and in its original packaging.
Return procedure for NLV27WZ07DFT2G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NLV27WZ07DFT2G Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments

-
SN74LVC2G17DBVR
Texas Instruments

-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments

-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

