onsemi NLV37WZ17USG
- Part No.:
- NLV37WZ17USG
- Manufacturer:
- onsemi
- Package:
- 8-VFSOP (0.091", 2.30mm Width)
- Datasheet:
-
NLV37WZ17USG.pdf
- Description:
- IC BUFFER NON-INVERT 5.5V US8
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
NLV37WZ17USG from onsemi is a triple noninverting Schmitt-trigger buffer IC operating from 1.65 V to 5.5 V, delivering 3.2 ns typical propagation delay at 5 V, ±24 mA drive capability at 3.0 V, and overvoltage-tolerant inputs/outputs up to 5.5 V - used in noise-immune digital signal conditioning for automotive sensor interfaces and industrial control logic.
For engineers reviewing the NLV37WZ17USG datasheet, pinout, applications, or equivalent options, key selection criteria include Schmitt-trigger hysteresis (0.7 V typ. at 5.5 V), IOFF partial power-down support, AEC-Q100 qualification, US8 package footprint, and 125 °C max operating temperature.
Technical Context
The NLV37WZ17USG implements three independent noninverting Schmitt-trigger buffers with input hysteresis (VH = 0.7 V typ. at VCC = 5.5 V) to reject noise on slow or noisy signals. Each channel supports rail-to-rail input voltage (0–5.5 V) independent of supply, enabling mixed-voltage interfacing.
It features IOFF circuitry that disables output leakage when VCC = 0 V, allowing safe back-driving in partial-power-down systems. Propagation delay is specified across 1.65–5.5 V supply range and −55 °C to +125 °C ambient, with guaranteed performance under 15 pF load and 1 MΩ source impedance.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.65 V to 5.5 V - enables direct interface with 1.8 V, 2.5 V, 3.3 V, and 5 V logic families without level shifters. |
| tPD (Typ) | 3.2 ns at VCC = 5 V - ensures minimal timing skew in high-speed enable/control paths. |
| IOH/IOL | ±24 mA at VCC = 3.0 V - drives multiple standard CMOS loads or small capacitive buses directly. |
| Input Hysteresis | 0.7 V typical at VCC = 5.5 V - rejects >700 mV of input noise without false triggering. |
| IOFF Leakage | ≤10 µA at VCC = 0 V - prevents signal contention during system sleep or hot-swap events. |
| Operating Temp | −55 °C to +125 °C - qualified for under-hood automotive and extended-temperature industrial use. |
| ESD Rating | HBM: 2000 V - meets IEC 61000-4-2 Level 2 immunity requirements for board-level robustness. |
Pinout & Package
Supplied in an 8-pin US8 (Micro8™) surface-mount package (Case 493), 2.1 mm × 2.0 mm × 0.55 mm, with 0.5 mm pitch and exposed pad for thermal enhancement.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (A1) | Input Channel 1 | Schmitt-trigger input for first buffer; accepts 0–5.5 V regardless of VCC. |
| 2 (Y3) | Output Channel 3 | Noninverting buffered output for third channel; drives up to 24 mA sink/source. |
| 3 (A2) | Input Channel 2 | Schmitt-trigger input for second buffer; electrically isolated from other inputs. |
| 4 (GND) | Ground Reference | Primary return path for all internal logic and I/O; must be low-impedance for noise immunity. |
| 5 (Y2) | Output Channel 2 | Noninverting buffered output for second channel; compatible with 3.3 V or 5 V bus loading. |
| 6 (A3) | Input Channel 3 | Schmitt-trigger input for third buffer; supports slow-rise sensor signals (e.g., thermistor dividers). |
| 7 (Y1) | Output Channel 1 | Noninverting buffered output for first channel; matches input hysteresis threshold (VT+ = 3.6 V typ. at 5.5 V). |
| 8 (VCC) | Power Supply | Single positive supply input; powers all three buffers and internal hysteresis circuitry. |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger inputs | Provides 0.7 V typical hysteresis at 5.5 V to eliminate chatter on noisy or slowly transitioning signals (e.g., mechanical switch bounce or analog sensor outputs). |
| Overvoltage-tolerant I/O | Accepts inputs up to 5.5 V even when VCC = 1.65 V - enables direct connection to higher-voltage subsystems without external clamping diodes. |
| IOFF partial power-down | Automatically disables output drivers and limits leakage to ≤10 µA when VCC = 0 V - essential for hot-plug and multi-rail power sequencing. |
| AEC-Q100 qualified | Qualified to Grade 1 (−40 °C to +125 °C) per AEC-Q100 Rev H - validated for automotive body electronics, lighting, and powertrain sub-systems. |
| Low dynamic power | CPD = 11 pF at 5.5 V - reduces switching current consumption in high-frequency enable/control applications (e.g., PWM gate drivers). |
Applications
| Automotive Door Module Interface | Industrial PLC Input Conditioning |
|---|---|
Use Scenario: Conditioning signals from mechanical door latch switches subject to EMI and contact bounce in vehicle door modules. IC Role / Device Role / Timing Role: Triple Schmitt-trigger buffer providing noise-immune digital conversion of raw switch closures before MCU sampling. Use Value: Eliminates need for external RC filters or firmware debouncing; hysteresis ≥0.7 V rejects >700 mV conducted noise per ISO 11452-4. | Use Scenario: Converting slow-rising analog sensor outputs (e.g., 4–20 mA loop receivers or thermistor dividers) into clean digital logic levels for PLC input cards. IC Role / Device Role / Timing Role: Signal conditioner converting analog thresholds into robust CMOS-compatible logic transitions with defined VT+ and VT−. Use Value: Enables direct interface with 1.8 V/3.3 V FPGA or microcontroller GPIOs without level-shifting or external comparators. |
| Motor Control Enable Sequencing | Medical Infusion Pump Safety Logic |
Use Scenario: Synchronizing enable signals across multiple motor driver ICs where timing skew and noise immunity are critical for fault-free startup. IC Role / Device Role / Timing Role: Low-skew triple buffer distributing synchronized enable pulses with matched tPLH/tPHL (≤4.5 ns max at 5 V). Use Value: Reduces inter-driver timing mismatch to <1 ns (typ.), preventing shoot-through during power stage initialization. | Use Scenario: Isolating and validating safety-critical limit switch signals in Class II medical infusion pumps operating in electromagnetically noisy hospital environments. IC Role / Device Role / Timing Role: Fail-safe signal conditioner ensuring only valid, noise-suppressed transitions reach the pump's safety controller. Use Value: Meets IEC 60601-1 EMI immunity requirements via built-in hysteresis and 2 kV HBM ESD protection on all pins. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Schmitt-trigger buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MC74VHC14DT | Hex inverting Schmitt-trigger; 2.0 V–5.5 V VCC; no IOFF; 8-pin SOIC (not US8); 7.5 ns tPD min at 5 V. | Requires inversion logic rework; lacks partial power-down; larger footprint; not AEC-Q100 qualified. | Select when hex inverting function is needed and space allows SOIC; verify hysteresis (0.35 V typ.) suffices for noise margin. |
| SN74LVC1G17DBVR | Single noninverting Schmitt-trigger; 1.65 V–5.5 V VCC; IOFF supported; SOT-23-5; 4.5 ns tPD typ. at 3.3 V. | Single-channel only; requires three devices for triple functionality; higher per-channel cost and board area. | Select for space-constrained single-channel use; avoid when triple-channel integration, timing matching, or AEC-Q100 compliance is required. |
Compared with MC74VHC14DT and SN74LVC1G17DBVR, the NLV37WZ17USG uniquely delivers triple-channel Schmitt buffering with AEC-Q100 qualification, IOFF, and US8 footprint - reducing BOM count, PCB area, and qualification effort in automotive and industrial control designs.
Availability
NLV37WZ17USG is available at Aetrix Electronics and suitable for automotive body electronics, industrial PLC input modules, and medical device safety logic requiring stable component supply, long-term lifecycle support, and AEC-Q100-compliant sourcing.
Supply support for NLV37WZ17USG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier focused on energy-efficient electronics for automotive, industrial, cloud, medical, and IoT applications.
The NLV37WZ17USG belongs to onsemi's precision logic family designed specifically for noise-immune signal conditioning in harsh electromagnetic environments - targeting automotive subsystems, factory automation, and safety-critical instrumentation.
FAQ
What is the maximum input voltage rating for NLV37WZ17USG when VCC = 1.65 V?
The NLV37WZ17USG supports input voltages up to 5.5 V regardless of VCC level, including when VCC = 1.65 V. This overvoltage tolerance is explicitly specified in the Absolute Maximum Ratings table (VIN = −0.5 V to +6.5 V) and confirmed in the Recommended Operating Conditions (VIN = 0 to 5.5 V). The NLV37WZ17USG achieves this via internal clamp structures that protect the input transistors without requiring external components.
Does NLV37WZ17USG support partial power-down mode, and how is it implemented?
Yes, NLV37WZ17USG supports partial power-down via its IOFF feature. When VCC = 0 V, the output drivers are disabled and input/output leakage is limited to ≤10 µA (max), preventing signal contention on shared buses. This behavior is verified in the DC Electrical Characteristics table under IOFF Power Off Leakage Current and applies across the full temperature range. The NLV37WZ17USG does not require external control signals to activate IOFF - it engages automatically upon VCC removal.
What is the typical hysteresis voltage (VH) of NLV37WZ17USG at VCC = 5.5 V, and how does it affect noise rejection?
The typical hysteresis voltage (VH) of NLV37WZ17USG is 0.7 V at VCC = 5.5 V, as shown in the DC Electrical Characteristics table. This means the difference between VT+ (3.6 V typ.) and VT− (2.9 V typ.) provides a 700 mV noise margin, allowing the NLV37WZ17USG to reject transient spikes or EMI-induced fluctuations below that threshold without false triggering - critical for reliable operation in automotive and industrial settings.
Is NLV37WZ17USG pin-compatible with standard 74-series Schmitt-trigger buffers like 74HC14?
No, NLV37WZ17USG is not pin-compatible with 74HC14 or other legacy hex inverter packages. It uses an 8-pin US8 layout optimized for triple noninverting channels (A1/Y3/A2/GND/Y2/A3/Y1/VCC), whereas 74HC14 uses 14-pin DIP/SOIC with six inverting channels. The NLV37WZ17USG pinout is unique to its function and package; migration requires PCB redesign. Always verify pin mapping using Figure 2 in the official NLV37WZ17USG datasheet.
What packaging and marking information confirms NLV37WZ17USG is the automotive-grade variant?
The "−Q" suffix in the full orderable part number (NL37WZ17USG−Q) denotes the automotive-grade variant, which is AEC-Q100 qualified and PPAP capable. While the commercial NLV37WZ17USG shares the same US8 package and marking code "LX", the automotive version is distinguished by its qualification documentation, test reports, and controlled change management - not physical marking. The NLV37WZ17USG itself is the standard-grade part; for automotive use, specify NL37WZ17USG−Q per the Device Ordering Information table on page 6 of the datasheet.
NLV37WZ17USG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 37WZ
- Package/Case:
- 8-VFSOP (0.091", 2.30mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 3
- Number of Bits per Element:
- 1
- Input Type:
- Schmitt Trigger
- Output Type:
- Push-Pull
- Current - Output High, Low:
- 32mA, 32mA
- Voltage - Supply:
- 2.3V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- US8
NLV37WZ17USG FAQ
1.How can I place an order for NLV37WZ17USG through Aetrix?
Please submit a Request for Quotation (RFQ) for NLV37WZ17USG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NLV37WZ17USG reliable?
The price and inventory of NLV37WZ17USG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NLV37WZ17USG is usually 5 days.
3.What payment methods are accepted for NLV37WZ17USG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NLV37WZ17USG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NLV37WZ17USG?
NLV37WZ17USG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NLV37WZ17USG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NLV37WZ17USG?
For technical support, including NLV37WZ17USG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NLV37WZ17USG requirements.
6.How does Aetrix verify that NLV37WZ17USG is sourced from the original manufacturer or authorized distributors?
All NLV37WZ17USG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NLV37WZ17USG meets industry standards.
7.What is the process for return or replacement of NLV37WZ17USG?
All NLV37WZ17USG units undergo pre-shipment inspection (PSI). If there is an issue with NLV37WZ17USG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NLV37WZ17USG part is unused and in its original packaging.
Return procedure for NLV37WZ17USG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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