onsemi NLV74HC04ADTR2G
- Part No.:
- NLV74HC04ADTR2G
- Manufacturer:
- onsemi
- Category:
- Gates and Inverters
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
NLV74HC04ADTR2G.pdf
- Description:
- IC INVERTER 6CH 1-INP 14TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,500
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Product details
Overview
NLV74HC04ADTR2G from onsemi is a high-performance silicon-gate CMOS hex inverter IC, configured as six independent three-stage inverters in a single TSSOP-14 package. It operates across 2.0–6.0 V supply voltage, delivers 10 LSTTL load drive capability, and supports industrial temperature range (−55 °C to +125 °C), making it suitable for logic-level translation and signal conditioning in embedded control and sensor interface circuits.
For engineers reviewing the NLV74HC04ADTR2G datasheet, pinout, applications, or equivalent options, key selection criteria include supply voltage compatibility (2.0–6.0 V), propagation delay (13 ns @ 6.0 V), input/output voltage thresholds, thermal performance in TSSOP-14, and automotive-grade qualification status.
Technical Context
The NLV74HC04ADTR2G implements six identical CMOS inverter stages with three-transistor topology per stage, enabling rail-to-rail output swing and high noise immunity. Its inputs are compatible with standard CMOS outputs and-when pulled up-LSTTL outputs, supporting mixed-logic interfacing without level shifters.
It features low quiescent current (≤40 µA at 125 °C), maximum input capacitance of 10 pF, and power dissipation capacitance of 20 pF per inverter. The device meets JEDEC Std. No. 7A and is AEC-Q100 qualified for automotive applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 2.0 V to 6.0 V - Enables direct operation from 3.3 V or 5 V rails without regulation. |
| Propagation Delay (tPLH/tPHL) | 13 ns max @ VCC = 6.0 V - Supports >30 MHz toggle rates in clean digital paths. |
| Output Drive Strength | 10 LSTTL loads - Sufficient to drive multiple legacy TTL inputs or fan-out to parallel logic gates. |
| Input Leakage Current | ±1.0 µA max @ 125 °C - Ensures stable logic levels in high-impedance or battery-powered nodes. |
| Operating Temperature | −55 °C to +125 °C - Validated for under-hood automotive, industrial PLC, and outdoor equipment use. |
| Input Threshold (VIH/VIL) | VIH = 4.20 V, VIL = 1.80 V @ VCC = 6.0 V - Provides 1.2 V noise margin for robust switching in noisy environments. |
| Power Dissipation Capacitance | 20 pF per inverter - Used to calculate dynamic power: PD = CPD × VCC² × f + ICC × VCC. |
Pinout & Package
TSSOP-14 (Case 948G), 4.9 mm × 4.4 mm × 1.2 mm body, 0.65 mm pitch, Pb-free, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | A1 (Input) | First inverter input; accepts CMOS- or TTL-compatible logic levels with pull-up. |
| 2 | Y1 (Output) | Inverted output of A1; drives downstream CMOS/NMOS/TTL loads directly. |
| 3 | A2 (Input) | Second inverter input; electrically isolated from other inputs; no internal crosstalk. |
| 4 | Y2 (Output) | Inverted output of A2; same electrical specs as Y1; supports independent signal inversion. |
| 5 | A3 (Input) | Third inverter input; shares no internal nodes with A1/A2; enables true six-channel isolation. |
| 6 | Y3 (Output) | Inverted output of A3; matched timing and drive to other outputs. |
| 7 | GND | Ground reference for all logic and power domains; must be low-impedance for noise immunity. |
| 8 | Y4 (Output) | Inverted output of A4; pin 9 is A4 - layout follows alternating input-output pattern. |
| 9 | A4 (Input) | Fourth inverter input; positioned adjacent to Y4 for minimal trace length in PCB routing. |
| 10 | Y5 (Output) | Inverted output of A5; maintains <1 ns skew vs. Y4/Y6 under matched load conditions. |
| 11 | A5 (Input) | Fifth inverter input; supports asynchronous signal conditioning without shared bias paths. |
| 12 | Y6 (Output) | Inverted output of A6; final channel; fully specified for 25 mA sink/source per pin. |
| 13 | A6 (Input) | Sixth inverter input; electrically identical to A1–A5; no functional differentiation. |
| 14 | VCC | Positive supply rail; decoupling capacitor (0.1 µF) required within 5 mm for stable operation. |
Key Features
| Feature | Design Value |
|---|---|
| CMOS three-stage inverter architecture | Delivers rail-to-rail output swing and eliminates shoot-through current during transitions. |
| JEDEC Std. No. 7A compliance | Ensures interoperability with legacy LS-TTL systems and standardized test methodology. |
| AEC-Q100 Grade 1 qualification | Validated for automotive powertrain and chassis modules requiring −40 °C to +125 °C operation. |
| Pb-free, halogen-free, RoHS-compliant | Meets global environmental regulations and supports lead-free reflow soldering (260 °C peak). |
| High noise immunity | Input hysteresis and >1.2 V noise margin at 6 V supply suppress EMI-induced glitches. |
Applications
| Industrial Sensor Interface | Automotive Body Control Module |
|---|---|
|
Use Scenario: Inverting analog comparator outputs or open-collector sensor signals before feeding into microcontroller GPIOs. IC Role / Device Role / Timing Role: Signal polarity correction and level restoration for 3.3 V/5 V mixed-voltage sensor subsystems. Use Value: Eliminates need for discrete transistor inverters; reduces BOM count and improves timing predictability vs. RC-based inversion. |
Use Scenario: Driving LED indicators, relay drivers, or optocoupler inputs from MCU I/O pins with inverted logic polarity. IC Role / Device Role / Timing Role: Logic-level inversion and fan-out buffering for safety-critical status signaling in door lock or lighting control. Use Value: Guaranteed 10 LSTTL load drive ensures reliable activation of multiple parallel loads without external buffers. |
| Embedded Power Sequencing | Test Equipment Digital I/O Conditioning |
|
Use Scenario: Generating complementary enable/disable signals for multi-rail DC-DC converters in FPGA or ASIC power management. IC Role / Device Role / Timing Role: Synchronized active-low reset generation and rail sequencing control with sub-15 ns delay matching. Use Value: Tight propagation delay matching (<2 ns skew between channels) prevents race conditions during power-up/down sequences. |
Use Scenario: Converting bidirectional bus signals or cleaning up slow-rise/fall waveforms from legacy instrumentation interfaces. IC Role / Device Role / Timing Role: Waveform sharpening and logic-level regeneration for GPIB, RS-232, or custom test fixture control lines. Use Value: 10 pF input capacitance and fast transition times (13 ns) preserve signal integrity up to 25 MHz in automated test setups. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar hex inverter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MC74HC04ADR2G | SOIC-14 package (7.5 mm × 5.0 mm); higher thermal resistance (116 °C/W vs. 150 °C/W); identical electrical specs. | Better suited for through-hole prototyping or legacy board designs with SOIC footprints. | Select when board space allows larger footprint and thermal design prioritizes lower junction rise over density. |
| SN74HC04DR | TI-manufactured; same logic function and pinout; VIH/VIL thresholds differ slightly (VIH = 3.15 V @ 4.5 V vs. onsemi's 3.15 V). | Validated in TI-specific reference designs; may require revalidation for AEC-Q100 automotive use. | Choose for TI ecosystem integration or dual-sourcing where automotive qualification is not required. |
Compared with MC74HC04ADR2G, NLV74HC04ADTR2G offers 35% smaller PCB area and better thermal performance in airflow-constrained enclosures; versus SN74HC04DR, it provides guaranteed AEC-Q100 Grade 1 qualification and tighter production lot traceability for automotive OEM programs.
Availability
NLV74HC04ADTR2G is available at Aetrix Electronics and suitable for industrial sensor interface, automotive body control, and embedded power sequencing requiring stable component supply, long-term lifecycle support, and AEC-Q100-compliant sourcing.
Supply support for NLV74HC04ADTR2G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power, analog, sensing, and connectivity solutions for automotive, industrial, and cloud infrastructure markets.
The NLV74HC04ADTR2G belongs to the MC74HC04A family, designed specifically for high-reliability logic inversion in harsh-environment applications where wide supply range, temperature resilience, and automotive qualification are mandatory.
FAQ
What is the maximum operating frequency supported by NLV74HC04ADTR2G?
NLV74HC04ADTR2G does not specify a maximum clock frequency, but its 13 ns maximum propagation delay at 6.0 V implies reliable operation up to approximately 30 MHz in clean, low-load digital paths. Actual usable frequency depends on capacitive loading, supply stability, and PCB layout; for sustained 25 MHz toggling, ensure ≤30 pF total load capacitance and proper decoupling.
Is NLV74HC04ADTR2G pin-compatible with standard LS04 or MC14069 devices?
Yes, NLV74HC04ADTR2G is identical in pinout to both the 74LS04 and MC14069 hex inverters, enabling drop-in replacement in existing designs. However, voltage-level compatibility must be verified: NLV74HC04ADTR2G requires 2.0–6.0 V supply and exhibits CMOS input thresholds, unlike TTL's 2.0 V VIH minimum - external pull-ups may be needed for LS04 substitution.
Does NLV74HC04ADTR2G support mixed-voltage interfacing between 3.3 V and 5 V systems?
Yes, NLV74HC04ADTR2G supports mixed-voltage operation: its inputs accept 3.3 V logic as valid HIGH when VCC = 5 V (VIH = 3.15 V min), and its outputs swing rail-to-rail, delivering ~3.3 V HIGH when VCC = 3.3 V. For 5 V → 3.3 V level shifting, add series resistors or clamp diodes to protect downstream 3.3 V inputs.
What is the meaning of "NLV" prefix in NLV74HC04ADTR2G?
The "NLV" prefix denotes onsemi's Automotive and Industrial Grade product line, indicating enhanced screening, extended temperature range (−55 °C to +125 °C), and AEC-Q100 qualification. NLV74HC04ADTR2G is not a commercial-grade HC04 variant - it undergoes additional reliability testing and lot traceability per automotive PPAP requirements.
Can unused inputs on NLV74HC04ADTR2G be left floating?
No, unused inputs on NLV74HC04ADTR2G must never be left floating. Per the datasheet, all unused inputs must be tied to a defined logic level - either VCC or GND - to prevent increased supply current, oscillation, or erratic output behavior due to noise coupling. Floating inputs can cause excessive ICC and thermal instability, especially at temperature extremes.
NLV74HC04ADTR2G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 74HC
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Inverter
- Number of Circuits:
- 6
- Number of Inputs:
- 1
- Features:
- -
- Voltage - Supply:
- 2V ~ 6V
- Current - Quiescent (Max):
- 1 µA
- Current - Output High, Low:
- 5.2mA, 5.2mA
- Input Logic Level - Low:
- 0.5V ~ 1.8V
- Input Logic Level - High:
- 1.5V ~ 4.2V
- Max Propagation Delay @ V, Max CL:
- 19ns @ 6V, 50pF
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-TSSOP
NLV74HC04ADTR2G FAQ
1.How can I place an order for NLV74HC04ADTR2G through Aetrix?
Please submit a Request for Quotation (RFQ) for NLV74HC04ADTR2G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NLV74HC04ADTR2G reliable?
The price and inventory of NLV74HC04ADTR2G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NLV74HC04ADTR2G is usually 5 days.
3.What payment methods are accepted for NLV74HC04ADTR2G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NLV74HC04ADTR2G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NLV74HC04ADTR2G?
NLV74HC04ADTR2G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NLV74HC04ADTR2G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NLV74HC04ADTR2G?
For technical support, including NLV74HC04ADTR2G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NLV74HC04ADTR2G requirements.
6.How does Aetrix verify that NLV74HC04ADTR2G is sourced from the original manufacturer or authorized distributors?
All NLV74HC04ADTR2G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NLV74HC04ADTR2G meets industry standards.
7.What is the process for return or replacement of NLV74HC04ADTR2G?
All NLV74HC04ADTR2G units undergo pre-shipment inspection (PSI). If there is an issue with NLV74HC04ADTR2G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NLV74HC04ADTR2G part is unused and in its original packaging.
Return procedure for NLV74HC04ADTR2G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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