onsemi NLV74HC125ADR2G
- Part No.:
- NLV74HC125ADR2G
- Manufacturer:
- onsemi
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
NLV74HC125ADR2G.pdf
- Description:
- IC BUFFER NON-INVERT 6V 14SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:4,666
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Product details
Overview
NLV74HC125ADR2G from onsemi is a quad 3-state noninverting buffer IC designed for bus-oriented systems, featuring four independent active-low output enables, 2.0–6.0 V operation, ±35 mA output drive per pin, and SOIC-14 packaging. It interfaces directly with CMOS, NMOS, and TTL loads and supports memory address drivers and clock distribution in industrial control and instrumentation.
For engineers reviewing the NLV74HC125ADR2G datasheet, pinout, applications, or equivalent options, key selection criteria include its active-low OE architecture, 15 LSTTL load drive capability, guaranteed propagation delay ≤23 ns at 4.5 V, and AEC-Q100 qualification for automotive-qualified variants (e.g., NLV74HC125ADR2G−Q).
Technical Context
The NLV74HC125ADR2G implements four identical noninverting buffer channels, each with an independent active-low output enable (OE1–OE4). Its logic function follows Y = A when OE = L, and Y = high-impedance when OE = H - enabling bidirectional bus control without external direction signals.
It uses high-performance silicon-gate CMOS technology compliant with JEDEC Std No. 7A, delivering low input current (±0.1 µA max), high noise immunity, and compatibility with standard CMOS outputs - with pullup resistors enabling LSTTL interfacing. The device operates across –55°C to +125°C, supporting extended industrial and automotive temperature ranges.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 2.0 V to 6.0 V - supports wide-input rail designs including 3.3 V and 5 V systems without level shifters. |
| Output Drive Capability | ±35 mA per pin - drives up to 15 LSTTL loads, sufficient for fanout into multiple downstream logic gates or bus lines. |
| Propagation Delay (A→Y) | ≤23 ns at VCC = 4.5 V, TA = 85°C - ensures timing-critical bus buffering with predictable latency in real-time control paths. |
| 3-State Leakage Current | ±5.0 µA max at 85°C - minimizes unintended current flow during high-impedance state, critical for low-power standby modes. |
| Operating Temperature | –55°C to +125°C - qualified for under-hood automotive, industrial PLC, and outdoor embedded applications. |
| Input Capacitance | 10 pF max - reduces capacitive loading on driving sources, preserving signal integrity in high-speed parallel buses. |
| Quiescent Supply Current | 40 µA max at 85°C - enables low-static-power operation in always-on subsystems like sensor interface hubs. |
Pinout & Package
Package: SOIC-14 (Case 751A), 3.9 mm × 8.7 mm body, 1.27 mm pitch, Pb-free, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 10, 13 | Input A1–A4 | Noninverting data inputs; accept CMOS- or TTL-compatible logic levels depending on external biasing. |
| 2, 5, 11, 14 | Output Enable OE1–OE4 | Active-low enables; pulling any OE low activates corresponding Y output; high places Y in high-Z. |
| 3, 6, 12, 9 | Output Y1–Y4 | Buffered noninverted outputs; tri-state capable, suitable for shared bus arbitration and multiplexing. |
| 7 | GND | Ground reference for all I/O and internal circuitry; must be low-impedance connection to minimize noise coupling. |
| 14 | VCC | Positive supply rail; decoupling capacitor (0.1 µF ceramic) required within 5 mm of pin for stable switching performance. |
Key Features
| Feature | Design Value |
|---|---|
| Quad independent 3-state buffers | Enables four isolated data paths with individual enable control - ideal for selective bus segment activation in multi-master systems. |
| Active-low output enables | Matches legacy LS125 pinout and simplifies integration with open-collector or active-low control logic without inverters. |
| High noise immunity | CMOS input structure provides >40% VCC noise margin - resists EMI in motor-drive or power-conversion adjacent layouts. |
| AEC-Q100 qualified variant available | NLV74HC125ADR2G−Q meets automotive stress testing requirements - supports functional safety-aware designs in ADAS domain controllers. |
| Pb-free, Halogen Free/BFR Free | Complies with RoHS Directive 2011/65/EU and JEDEC JS709E - satisfies environmental compliance for global OEM BOMs. |
Applications
| Industrial PLC Backplane | Automotive Body Control Module |
|---|---|
|
Use Scenario: Isolating and buffering address/data lines between microcontroller and peripheral ASICs on a 100 mm backplane with mixed-voltage domains. IC Role / Device Role / Timing Role: Quad noninverting buffer with per-channel OE control manages bidirectional bus contention and prevents signal reflection during hot-swap events. Use Value: 23 ns max propagation delay ensures setup/hold timing margins are maintained across 10 MHz address strobes; ±35 mA drive sustains signal integrity over 15 cm traces. |
Use Scenario: Enabling/disabling CAN transceiver TX/RX lines and sensor interface muxes based on ignition state in a BCM with 12 V battery input. IC Role / Device Role / Timing Role: Level-shifting and bus-isolation buffer that interfaces 3.3 V MCU GPIOs to 5 V sensor buses while providing fail-safe high-Z isolation during sleep mode. Use Value: –55°C to +125°C operation guarantees reliability in engine bay environments; <10 pF input capacitance avoids degrading rise time of 500 kHz PWM sensor clocks. |
| Medical Infusion Pump Controller | Test Equipment Signal Routing |
|
Use Scenario: Routing step/direction signals from FPGA to stepper motor drivers while isolating fault feedback lines from main control logic. IC Role / Device Role / Timing Role: Safety-isolated buffer stage with independent OE pins allows dynamic reconfiguration of motor axis control paths without CPU intervention. Use Value: 40 µA max ICC at 85°C minimizes self-heating in sealed enclosures; high-impedance state leakage <5 µA prevents false triggering of safety interlocks. |
Use Scenario: Multiplexing calibration reference signals between DMM front-end and ADC test points in automated bench instrumentation. IC Role / Device Role / Timing Role: Precision signal gate with matched propagation delays across all four channels ensures phase-coherent routing of 100 kHz sine references. Use Value: Matched tPLH/tPHL ≤23 ns and <15 pF Cout preserve signal fidelity and reduce jitter accumulation in cascaded routing paths. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 3-state noninverting buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MC74HC125ADR2G | Same logic function and pinout; differs only in temperature grade (–55°C to +125°C vs. –40°C to +85°C for standard HC125A). | Not AEC-Q100 qualified; lacks automotive change control and PPAP documentation support. | Select MC74HC125ADR2G for commercial/industrial use where extended temp range suffices but automotive qualification is unnecessary. |
| SN74HC125DR | TI part with identical function and SOIC-14 package; VIH/VIL thresholds differ slightly (VIH min = 3.15 V @ VCC = 4.5 V vs. onsemi's 3.15 V). | Not qualified to AEC-Q100; no −Q automotive variant; different moisture sensitivity level (MSL 1 vs. onsemi's MSL 1). | Choose SN74HC125DR when sourcing from TI's authorized channel is preferred and automotive traceability is not required. |
Compared with NLV74HC125ADR2G, MC74HC125ADR2G offers identical electrical behavior but lacks automotive qualification, while SN74HC125DR provides equivalent functionality with minor input threshold variance and no AEC-Q100 support - making NLV74HC125ADR2G the only option meeting both extended temperature and automotive compliance requirements in one package.
Availability
NLV74HC125ADR2G is available at Aetrix Electronics and suitable for industrial PLC backplanes, automotive body control modules, medical infusion pump controllers, and test equipment signal routing requiring stable component supply across extended temperature and automotive-qualified lifecycles.
Supply support for NLV74HC125ADR2G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power, analog, sensing, and connectivity solutions for automotive, industrial, cloud, and IoT applications.
NLV74HC125ADR2G belongs to the NLV74HC logic family - engineered for high-reliability automotive and industrial environments, emphasizing extended temperature operation, AEC-Q100 compliance, and robust ESD tolerance.
FAQ
What is the operating voltage range for NLV74HC125ADR2G?
The NLV74HC125ADR2G operates from 2.0 V to 6.0 V DC supply voltage, supporting both 3.3 V and 5 V logic systems. This range is validated across the full –55°C to +125°C temperature envelope, with guaranteed performance per the onsemi datasheet revision 16 (January 2024). The NLV74HC125ADR2G maintains specified VOH, VOL, and propagation delay within this range.
Does NLV74HC125ADR2G support automotive applications?
Yes - the NLV74HC125ADR2G is the automotive-grade variant of the MC74HC125A, qualified to AEC-Q100 Grade 1 (–40°C to +125°C ambient) and PPAP-capable. Its marking includes the "−Q" suffix in the automotive version (NLV74HC125ADR2G−Q), and it undergoes additional process controls and change management per onsemi's automotive quality system. The NLV74HC125ADR2G itself is rated for –55°C to +125°C and used in under-hood and chassis modules.
How many independent output enables does NLV74HC125ADR2G have?
The NLV74HC125ADR2G features four independent active-low output enables (OE1 through OE4), one per buffer channel. Each OE pin controls only its associated output (Y1–Y4), allowing selective activation of individual data paths without affecting others - a key capability for dynamic bus segmentation in multi-peripheral systems. This architecture matches the LS125 pinout and is confirmed in Figure 2 and the Function Table of the NLV74HC125ADR2G datasheet.
What is the maximum propagation delay of NLV74HC125ADR2G at 5 V?
At VCC = 5.0 V and TA = 85°C, the NLV74HC125ADR2G has a maximum propagation delay (tPLH/tPHL) of 23 ns from input A to output Y, and 30 ns from OE to Y (tPLZ/tPHZ). These values are specified in the AC Electrical Characteristics table for the MC74HC125A family and apply directly to NLV74HC125ADR2G per onsemi's product definition. The NLV74HC125ADR2G achieves this performance using silicon-gate CMOS technology with 72 FETs per device.
Is NLV74HC125ADR2G pin-compatible with standard 74LS125 devices?
Yes - the NLV74HC125ADR2G is pin-compatible with the 74LS125 and 74LS126, as explicitly stated in the datasheet: "identical in pinout to the LS125 and LS126." Pin assignments for inputs (A1–A4), outputs (Y1–Y4), enables (OE1–OE4), VCC, and GND match exactly. However, NLV74HC125ADR2G requires appropriate pullup resistors for LSTTL compatibility and operates at higher voltage ranges than bipolar LS logic.
NLV74HC125ADR2G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 74HC
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 7.8mA, 7.8mA
- Voltage - Supply:
- 2V ~ 6V
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SOIC
NLV74HC125ADR2G FAQ
1.How can I place an order for NLV74HC125ADR2G through Aetrix?
Please submit a Request for Quotation (RFQ) for NLV74HC125ADR2G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NLV74HC125ADR2G reliable?
The price and inventory of NLV74HC125ADR2G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NLV74HC125ADR2G is usually 5 days.
3.What payment methods are accepted for NLV74HC125ADR2G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NLV74HC125ADR2G transactions.
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4.How is shipping managed for NLV74HC125ADR2G?
NLV74HC125ADR2G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NLV74HC125ADR2G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NLV74HC125ADR2G?
For technical support, including NLV74HC125ADR2G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NLV74HC125ADR2G requirements.
6.How does Aetrix verify that NLV74HC125ADR2G is sourced from the original manufacturer or authorized distributors?
All NLV74HC125ADR2G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NLV74HC125ADR2G meets industry standards.
7.What is the process for return or replacement of NLV74HC125ADR2G?
All NLV74HC125ADR2G units undergo pre-shipment inspection (PSI). If there is an issue with NLV74HC125ADR2G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NLV74HC125ADR2G part is unused and in its original packaging.
Return procedure for NLV74HC125ADR2G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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