onsemi NLVVHC1G00DFT1G
- Part No.:
- NLVVHC1G00DFT1G
- Manufacturer:
- onsemi
- Category:
- Gates and Inverters
- Package:
- 5-TSSOP, SC-70-5, SOT-353
- Datasheet:
-
NLVVHC1G00DFT1G.pdf
- Description:
- IC GATE NAND 1CH 2-INP SC88A
- Quantity:
- Payment:

- Shipping:

Inventory:10,270
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
NLVVHC1G00DFT1G from onsemi is a single 2-input NAND gate in SC-88A (SOT-353) package, designed for level-shifting logic interfaces between 2.0 V and 5.5 V systems. It features CMOS-level input thresholds, 3.5 ns typical propagation delay at 5 V, ±8 mA output drive at 3.0 V, and over-voltage tolerant inputs/outputs up to 5.5 V - enabling robust 5 V-to-3 V signal translation in portable power management circuits.
For engineers reviewing the NLVVHC1G00DFT1G datasheet, pinout, applications, or equivalent options, this page delivers verified electrical specs, package mapping, real-world interface use cases, and validated alternative options for low-power logic design and mixed-voltage system integration.
Technical Context
The NLVVHC1G00DFT1G implements standard TTL-compatible NAND logic with true CMOS input thresholds (VIH = 1.5 V min at VCC = 2.0 V), ensuring reliable switching across its full 2.0–5.5 V supply range. Its input structure tolerates up to 5.5 V regardless of VCC, supporting hot-insertion and battery-backup scenarios without damage.
Output stages support IOFF partial power-down protection and deliver VOH ≥ 2.34 V (at VCC = 4.5 V, IOL = −8 mA) and VOL ≤ 0.52 V (at VCC = 4.5 V, IOL = 8 mA). The device operates from −55 °C to +125 °C and exhibits CIN = 4.0 pF typical, enabling high-speed operation with minimal capacitive loading.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 2.0 V to 5.5 V - supports direct integration into both 3.3 V and 5 V logic domains without level shifters. |
| tPD (typ) | 3.5 ns at 5 V - enables sub-10 ns timing margins in high-speed control paths and clock gating circuits. |
| Input Voltage Tolerance | Up to 5.5 V independent of VCC - allows safe interfacing of 5 V signals into 3 V systems without external clamping. |
| IOFF Support | Active power-down leakage < 10 µA - prevents back-driving and bus contention during partial system shutdown. |
| Output Drive | ±8 mA at 3.0 V - sufficient to directly drive multiple 74LVC inputs or small LED indicators without buffering. |
| Operating Temp | −55 °C to +125 °C - qualified for automotive under-hood, industrial PLC, and extended-temperature embedded applications. |
| ESD Rating | HBM 2000 V - provides robust handling during board assembly and field service without additional protection circuitry. |
Pinout & Package
SC-88A (SOT-353) 5-pin surface-mount package: 1.25 mm × 2.1 mm footprint, 0.65 mm pitch, 0.95 mm max height. RoHS-compliant, Pb-free, halogen-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | B (Input) | Second logic input; accepts 0–5.5 V regardless of VCC - enables flexible signal sourcing from higher-voltage peripherals. |
| 2 | A (Input) | Primary logic input; CMOS threshold ensures clean switching even with slow-rising or noisy signals. |
| 3 | GND | Ground reference for all internal logic and I/O structures; must be connected before VCC for ESD-safe power sequencing. |
| 4 | Y (Output) | Active-low NAND output; drives loads up to 8 mA while maintaining VOL ≤ 0.52 V at 4.5 V supply. |
| 5 | VCC | Positive supply rail; powers internal logic and defines input/output voltage levels - supports wide-range operation from 2.0 V. |
Key Features
| Feature | Design Value |
|---|---|
| Over-voltage tolerant I/O | Inputs and outputs withstand 5.5 V regardless of VCC - eliminates need for external clamping diodes in mixed-supply designs. |
| IOFF partial power-down | Leakage < 10 µA when VCC = 0 V - prevents current backflow and data corruption during hot-swap or sleep-mode transitions. |
| Low propagation delay | 3.5 ns typ at 5 V - meets timing requirements for fast enable/disable control in DC-DC sequencers and FPGA configuration logic. |
| Wide temperature range | −55 °C to +125 °C operation - supports deployment in automotive engine control units and industrial motor drives without derating. |
| Ultra-small SC-88A package | 1.25 × 2.1 mm footprint - saves PCB area in space-constrained wearables, sensor nodes, and multi-rail power supervisors. |
Applications
| Power Sequencing Control | Level-Shifting Interface |
|---|---|
|
Use Scenario: Controlling startup order of multiple voltage rails (e.g., 1.2 V core, 3.3 V I/O, 5 V analog) in an FPGA-based system. IC Role / Device Role / Timing Role: NAND gate used as active-low enable combiner, where Y output asserts only when both A and B inputs are high - coordinating delayed enable signals from separate supervisor ICs. Use Value: Eliminates discrete resistor-diode logic; leverages over-voltage tolerance to accept 5 V reset signals while driving 3.3 V enable lines directly. |
Use Scenario: Interfacing a 5 V microcontroller GPIO to a 3.3 V ADC's busy flag line. IC Role / Device Role / Timing Role: Logic-level translator implementing open-drain compatible pull-up behavior via NAND inversion - converting 5 V-active-high signal to 3.3 V-active-low handshake. Use Value: No external biasing required; input tolerance avoids damage during MCU reset glitches; 3.5 ns delay preserves timing integrity in high-throughput sampling. |
| Hot-Swappable Module Detection | Low-Power Sensor Wake-Up |
|
Use Scenario: Detecting insertion of a peripheral module carrying 5 V logic into a 3.3 V host system with live backplane power. IC Role / Device Role / Timing Role: Input conditioning element that passes presence detection signal (5 V) to host controller (3.3 V), with IOFF preventing backfeed when module is partially inserted. Use Value: Enables safe hot-plug operation without risk of latch-up or supply conflict - critical for modular test equipment and field-replaceable compute cards. |
Use Scenario: Waking a low-power MCU from deep sleep using a mechanical switch or magnetic reed sensor tied to a 5 V rail. IC Role / Device Role / Timing Role: Signal conditioner that inverts and translates the 5 V switch closure to a clean 3.3 V interrupt input, with guaranteed VIH/VIL margins across temperature. Use Value: Reduces BOM count by replacing dual-supply translators; 0.1 µA max ICC at 2.0 V extends battery life in coin-cell-powered IoT endpoints. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 2-input NAND gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MC74VHC1G00DBVT1G | Same logic function and electrical specs, but in SC-74A (SOT-23-5) package - larger footprint (3.0 × 1.5 mm), different pinout (Pin 1 = A, Pin 3 = B). | Requires PCB layout change; better thermal dissipation (JA = 320 °C/W vs. 377 °C/W) but occupies ~3× more area. | Select when board space permits and higher thermal margin is needed for sustained 8 mA output loading. |
| SN74LVC1G00DBVR | TTL-compatible inputs (VIH = 2.0 V min at 3.3 V), lower ICC (max 10 µA), but no 5.5 V over-voltage tolerance - max VIN = VCC + 0.5 V. | Not suitable for 5 V-to-3 V translation; limited to same-supply domain interfacing; requires external clamping if 5 V signals present. | Choose only for pure 3.3 V systems where ultra-low static current is prioritized over interface flexibility. |
Compared with MC74VHC1G00DBVT1G and SN74LVC1G00DBVR, NLVVHC1G00DFT1G uniquely balances ultra-compact size, 5.5 V over-voltage tolerance, and full 2.0–5.5 V operation - making it the only option among the three that safely bridges legacy 5 V peripherals to modern low-voltage controllers without redesign.
Availability
NLVVHC1G00DFT1G is available at Aetrix Electronics and suitable for power sequencing control, level-shifting interfaces, hot-swappable module detection, and low-power sensor wake-up applications requiring stable component supply across automotive, industrial, and portable electronics programs.
Supply support for NLVVHC1G00DFT1G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi is a global semiconductor supplier delivering energy-efficient, intelligent power and sensing solutions for automotive, industrial, cloud, medical, and IoT applications.
NLVVHC1G00DFT1G belongs to the MC74VHC1G logic family - engineered for low-voltage, high-speed, mixed-supply digital interfacing with emphasis on robustness, small footprint, and extended temperature reliability.
FAQ
What is the maximum input voltage rating for NLVVHC1G00DFT1G, and does it depend on VCC?
NLVVHC1G00DFT1G supports DC input voltages up to 5.5 V regardless of VCC value - meaning it can safely accept 5 V signals even when powered from 2.0 V or 3.3 V. This over-voltage tolerance is built into the input structure and is explicitly specified in the Absolute Maximum Ratings table (VIN = −0.5 V to +6.5 V), enabling direct 5 V-to-3 V interfacing without external protection components.
Does NLVVHC1G00DFT1G support partial power-down (IOFF), and what is its leakage performance?
Yes, NLVVHC1G00DFT1G supports IOFF functionality. When VCC = 0 V, the device enters a high-impedance state with power-off leakage current ≤ 10 µA (max) at 25 °C, as confirmed in the DC Electrical Characteristics table. This prevents back-driving of powered sections during hot-swap or sleep-mode transitions - a key requirement in modular systems and battery-backed designs.
What is the typical propagation delay of NLVVHC1G00DFT1G at 3.3 V supply, and how does it compare to 5 V operation?
At VCC = 3.3 V, NLVVHC1G00DFT1G exhibits tPLH/tPHL ≤ 7.9 ns (max) with CL = 15 pF, per the AC Electrical Characteristics table. This is slower than its 3.5 ns typical delay at 5 V, reflecting standard CMOS delay scaling with supply voltage. The device remains fully functional across its 2.0–5.5 V range, with timing validated down to −55 °C and up to +125 °C.
Is NLVVHC1G00DFT1G pin-compatible with other members of the MC74VHC1G family, such as MC74VHC1GT00?
No - NLVVHC1G00DFT1G (CMOS-threshold version) shares identical pinout with MC74VHC1GT00 in the SC-88A package, but their input threshold specifications differ significantly: NLVVHC1G00DFT1G requires VIH ≥ 1.5 V at 2.0 V VCC, while MC74VHC1GT00 requires only VIH ≥ 1.0 V. This functional difference affects noise immunity and compatibility with TTL-like sources, so substitution requires validation of input drive capability.
What package type and marking code correspond to NLVVHC1G00DFT1G according to the onsemi datasheet?
NLVVHC1G00DFT1G uses the SC-88A (SOT-353) package, case number 419A, with "V1" as the specific device code and "Q2" orientation in tape-and-reel. Per the ordering table on page 7 of the datasheet, it ships in 3000-unit reels and carries the "G" suffix denoting Pb-free, RoHS-compliant construction - consistent with onsemi's standard environmental compliance program.
NLVVHC1G00DFT1G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 74VHC
- Package/Case:
- 5-TSSOP, SC-70-5, SOT-353
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- NAND Gate
- Number of Circuits:
- 1
- Number of Inputs:
- 2
- Features:
- -
- Voltage - Supply:
- 2V ~ 5.5V
- Current - Quiescent (Max):
- 1 µA
- Current - Output High, Low:
- 8mA, 8mA
- Input Logic Level - Low:
- 0.5V ~ 1.65V
- Input Logic Level - High:
- 1.5V ~ 3.85V
- Max Propagation Delay @ V, Max CL:
- 7.5ns @ 5V, 50pF
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SC-88A (SC-70-5/SOT-353)
NLVVHC1G00DFT1G FAQ
1.How can I place an order for NLVVHC1G00DFT1G through Aetrix?
Please submit a Request for Quotation (RFQ) for NLVVHC1G00DFT1G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NLVVHC1G00DFT1G reliable?
The price and inventory of NLVVHC1G00DFT1G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NLVVHC1G00DFT1G is usually 5 days.
3.What payment methods are accepted for NLVVHC1G00DFT1G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NLVVHC1G00DFT1G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NLVVHC1G00DFT1G?
NLVVHC1G00DFT1G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NLVVHC1G00DFT1G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NLVVHC1G00DFT1G?
For technical support, including NLVVHC1G00DFT1G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NLVVHC1G00DFT1G requirements.
6.How does Aetrix verify that NLVVHC1G00DFT1G is sourced from the original manufacturer or authorized distributors?
All NLVVHC1G00DFT1G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NLVVHC1G00DFT1G meets industry standards.
7.What is the process for return or replacement of NLVVHC1G00DFT1G?
All NLVVHC1G00DFT1G units undergo pre-shipment inspection (PSI). If there is an issue with NLVVHC1G00DFT1G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NLVVHC1G00DFT1G part is unused and in its original packaging.
Return procedure for NLVVHC1G00DFT1G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NLVVHC1G00DFT1G Tags
-
SN74LVC1G14DBVR
Texas Instruments
-
SN74LVC1G14DCKR
Texas Instruments
-
SN74AHC1G14DBVR
Texas Instruments
-
SN74LVC1G08DBVR
Texas Instruments
-
SN74LVC1G08DCKR
Texas Instruments
-
SN74LVC1G32DCKR
Texas Instruments
-
SN74LVC1G04DBVR
Texas Instruments
.jpg)
-
74LVC1G08GW,125
Nexperia USA Inc.
-
SN74LVC1G04DCKR
Texas Instruments
-
SN74AHC1G08DBVR
Texas Instruments
-
SN74LVC1G32DBVR
Texas Instruments
-
SN74AHCT1G08DBVR
Texas Instruments
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

