onsemi NLVVHC1G132DFT2G
- Part No.:
- NLVVHC1G132DFT2G
- Manufacturer:
- onsemi
- Category:
- Gates and Inverters
- Package:
- 5-TSSOP, SC-70-5, SOT-353
- Datasheet:
-
NLVVHC1G132DFT2G.pdf
- Description:
- IC GATE NAND 1CH 2-INP SC88A
- Quantity:
- Payment:

- Shipping:

Inventory:2,210
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
NLVVHC1G132DFT2G from onsemi is a single 2-input NAND Schmitt-trigger logic gate in SC-88A (SOT-353) package, designed for noise-immune signal conditioning in mixed-voltage systems. It operates from 2.0 V to 5.5 V, delivers 3.6 ns typical propagation delay at 5 V, features CMOS-level input thresholds (VT+ = 2.2–3.85 V at VCC = 3.0–5.5 V), and supports 5.5 V overvoltage-tolerant inputs/outputs - enabling reliable 5 V-to-3 V interface applications in industrial control and sensor signal conditioning.
For engineers reviewing the NLVVHC1G132DFT2G datasheet, pinout, applications, or equivalent options, key selection criteria include Schmitt-trigger hysteresis (0.30–0.50 V typ), IOFF partial power-down protection, ±8 mA drive capability at 3.0 V, and AEC-Q100 qualification for automotive-grade reliability.
Technical Context
The NLVVHC1G132DFT2G implements a single 2-input NAND function with Schmitt-trigger inputs, providing hysteresis (VH = 0.30–0.50 V typ) to reject analog noise on slow or noisy digital signals. Its input structure tolerates up to 5.5 V regardless of VCC, allowing safe interfacing between 5 V legacy circuits and 3 V logic domains without level shifters.
It supports IOFF functionality - when VCC = 0 V, input/output leakage remains ≤10 µA - preventing back-driving and bus contention during partial power-down. Output drive strength is specified at ±4 mA and ±8 mA (VOL ≤ 0.1 V, VOH ≥ 2.9 V at VCC = 3.0 V), ensuring robust fan-out in low-power embedded systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 2.0 V to 5.5 V - enables operation across battery-powered (3.3 V), industrial (5 V), and mixed-supply systems |
| Propagation Delay | 3.6 ns typ at 5 V (CL = 15 pF) - supports high-speed signal conditioning in timing-critical paths |
| Input Hysteresis | 0.30–0.50 V typ (VCC = 3.0–5.5 V) - rejects up to ~500 mV of input noise without false triggering |
| Overvoltage Tolerance | Inputs/outputs rated to 5.5 V independent of VCC - eliminates need for external clamping diodes |
| IOFF Leakage | ≤10 µA at VCC = 0 V - prevents current backflow and bus contention during power sequencing |
| Output Drive | ±8 mA at 3.0 V (VOL ≤ 0.1 V, VOH ≥ 2.9 V) - drives multiple 74LVC inputs or small capacitive loads |
| Operating Temp | −55 °C to +125 °C - qualified for extended industrial and under-hood automotive environments |
Pinout & Package
Package: SC-88A (SOT-353), 5-pin surface-mount, 2.0 mm × 1.25 mm × 0.95 mm body, lead pitch 0.65 mm, RoHS-compliant, Pb-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Input B | Second NAND input; Schmitt-triggered, 5.5 V tolerant, VIH/VIL defined by CMOS thresholds |
| 2 | Input A | First NAND input; identical electrical behavior to Pin 1 |
| 3 | GND | Ground reference for logic and supply return; must be low-impedance for noise immunity |
| 4 | Output Y | NAND result (Y = NOT(A AND B)); push-pull output with ±8 mA drive and 5.5 V tolerance |
| 5 | VCC | Positive supply (2.0–5.5 V); powers internal logic and enables IOFF behavior when at 0 V |
Key Features
| Feature | Design Value |
|---|---|
| CMOS-level Schmitt trigger | VT+ = 2.2–3.85 V / VT− = 0.9–1.65 V (VCC = 3.0–5.5 V) - ensures clean switching on slow-rising sensor or switch inputs |
| 5.5 V overvoltage-tolerant I/O | Inputs and outputs withstand 5.5 V even at VCC = 2.0 V - enables direct connection to 5 V buses without level translation |
| IOFF partial power-down | Leakage ≤10 µA when VCC = 0 V - maintains isolation during hot-swap or multi-rail power sequencing |
| AEC-Q100 qualified | Qualified per Grade 1 (−40 °C to +125 °C) and PPAP-capable - suitable for automotive body electronics and ADAS subsystems |
| Low dynamic power | CPD = 8.0 pF - minimizes switching current (ICC(OPR) = CPD × VCC² × f + ICC) in battery-sensitive designs |
Applications
| Industrial Sensor Interface | Automotive Body Control |
|---|---|
Use Scenario: Conditioning noisy open-collector encoder or limit-switch outputs in PLC I/O modules. IC Role / Device Role / Timing Role: Schmitt-trigger NAND gate cleans slow, bouncing mechanical signals before microcontroller sampling. Use Value: Eliminates external RC filtering and software debouncing; hysteresis rejects >400 mV of EMI-induced noise on 24 V sensor lines stepped down to 3.3 V. |
Use Scenario: Debouncing door latch or seat position switches in vehicle body control units (BCUs). IC Role / Device Role / Timing Role: Single-gate NAND with IOFF isolates switch inputs during MCU sleep mode (VCC = 0 V). Use Value: Prevents back-current into powered-down MCU GPIOs; AEC-Q100 qualification ensures reliability across thermal cycling and vibration. |
| Power Sequencing Monitor | Legacy System Glue Logic |
Use Scenario: Detecting simultaneous presence of two regulated rails (e.g., 3.3 V and 5 V) to enable downstream circuitry. IC Role / Device Role / Timing Role: NAND gate acts as dual-rail power-good detector with noise margin via Schmitt inputs. Use Value: Built-in hysteresis avoids oscillation during rail ramp-up; 5.5 V tolerance allows direct connection to unregulated 5 V monitoring points. |
Use Scenario: Adapting TTL-level control signals from legacy instrumentation to modern 3.3 V FPGA I/O banks. IC Role / Device Role / Timing Role: Level-shifting interface using overvoltage-tolerant inputs and CMOS-compatible outputs. Use Value: No external resistors or translators needed; 3.6 ns propagation delay preserves timing integrity in control loops. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Schmitt-trigger NAND gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MC74VHC1G132DBVT1G | Same logic function and specs, but in SC-74A (SOT-23-5) package - 3.0 mm × 1.5 mm, larger footprint, higher thermal resistance (320 °C/W vs. 377 °C/W) | Preferred where board space permits larger pads or reworkability is prioritized over miniaturization | Select when SC-74A's mechanical robustness or compatibility with existing SOT-23 footprints outweighs SC-88A's size advantage |
| SN74LVC1G132DBVR | Lower VCC range (1.65–5.5 V), faster tPD (3.5 ns typ at 3.3 V), but no AEC-Q100 qualification and only 3.6 V max input tolerance | Suitable for commercial-grade portable electronics, not automotive or extended-temp industrial use | Choose for cost-sensitive consumer designs requiring tighter timing margins below 3.3 V, but avoid where 5.5 V tolerance or automotive qualification is mandatory |
Compared with MC74VHC1G132DBVT1G and SN74LVC1G132DBVR, the NLVVHC1G132DFT2G uniquely combines AEC-Q100 qualification, 5.5 V overvoltage tolerance, and SC-88A miniaturization - making it the only option among the three qualified for space-constrained automotive body electronics requiring robust mixed-voltage interfacing.
Availability
NLVVHC1G132DFT2G is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive body control modules, and power sequencing monitors requiring stable component supply, long-term lifecycle support, and AEC-Q100-compliant performance.
Supply support for NLVVHC1G132DFT2G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient silicon solutions for automotive, industrial, cloud, and IoT applications.
The NLVVHC1G132DFT2G belongs to the VHC1G ultra-small logic family, engineered for space-constrained, noise-prone environments where Schmitt-trigger noise immunity, mixed-voltage interoperability, and automotive-grade reliability are essential.
FAQ
What is the input threshold voltage range for NLVVHC1G132DFT2G at 3.3 V supply?
The NLVVHC1G132DFT2G has CMOS-level Schmitt-trigger inputs: VT+ (positive threshold) is 2.2 V min and 2.58 V typ, while VT− (negative threshold) is 0.9 V min and 1.5 V typ at VCC = 3.0 V. These values ensure ≥1.3 V hysteresis, enabling reliable rejection of noise on slow-rising signals such as mechanical switch closures or sensor outputs. The NLVVHC1G132DFT2G datasheet specifies these parameters across −55 °C to +125 °C.
Does NLVVHC1G132DFT2G support partial power-down operation?
Yes, the NLVVHC1G132DFT2G supports IOFF functionality: when VCC = 0 V, input and output leakage current is limited to ≤10 µA, preventing back-driving of powered-down system buses. This feature is confirmed in the DC Electrical Characteristics table of the NLVVHC1G132DFT2G datasheet and is critical for hot-swap and multi-rail power sequencing applications.
Is NLVVHC1G132DFT2G pin-compatible with MC74VHC1GT132 variants?
No, NLVVHC1G132DFT2G is not pin-compatible with MC74VHC1GT132 variants. While both share identical SC-88A pinout and package, they differ in input threshold architecture: NLVVHC1G132DFT2G uses CMOS-level thresholds (VT+ ≈ 2.2–3.85 V), whereas MC74VHC1GT132 uses TTL-level thresholds (VT+ ≈ 1.6–2.1 V). Substituting them requires validation of input signal levels and noise margin in the target application.
What is the maximum operating temperature range for NLVVHC1G132DFT2G?
The NLVVHC1G132DFT2G is rated for −55 °C to +125 °C operation, meeting AEC-Q100 Grade 1 requirements. This extended range is verified in the Recommended Operating Conditions table of the NLVVHC1G132DFT2G datasheet and supports deployment in under-hood automotive electronics, industrial motor controls, and outdoor infrastructure equipment.
Can NLVVHC1G132DFT2G safely interface a 5 V sensor output to a 3.3 V microcontroller input?
Yes, the NLVVHC1G132DFT2G can safely interface a 5 V sensor output to a 3.3 V microcontroller input: its inputs tolerate up to 5.5 V regardless of VCC, and its output swings rail-to-rail (VOH ≥ 2.9 V at VCC = 3.3 V), meeting 3.3 V logic-high requirements. This capability is explicitly documented in the Absolute Maximum Ratings and DC Electrical Characteristics sections of the NLVVHC1G132DFT2G datasheet.
NLVVHC1G132DFT2G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 74VHC
- Package/Case:
- 5-TSSOP, SC-70-5, SOT-353
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- NAND Gate
- Number of Circuits:
- 1
- Number of Inputs:
- 2
- Features:
- Schmitt Trigger
- Voltage - Supply:
- 2V ~ 5.5V
- Current - Quiescent (Max):
- 1 µA
- Current - Output High, Low:
- 8mA, 8mA
- Input Logic Level - Low:
- 0.65V ~ 1.45V
- Input Logic Level - High:
- 2.25V ~ 3.7V
- Max Propagation Delay @ V, Max CL:
- 9.7ns @ 5V, 50pF
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SC-88A (SC-70-5/SOT-353)
NLVVHC1G132DFT2G FAQ
1.How can I place an order for NLVVHC1G132DFT2G through Aetrix?
Please submit a Request for Quotation (RFQ) for NLVVHC1G132DFT2G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NLVVHC1G132DFT2G reliable?
The price and inventory of NLVVHC1G132DFT2G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NLVVHC1G132DFT2G is usually 5 days.
3.What payment methods are accepted for NLVVHC1G132DFT2G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NLVVHC1G132DFT2G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NLVVHC1G132DFT2G?
NLVVHC1G132DFT2G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NLVVHC1G132DFT2G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NLVVHC1G132DFT2G?
For technical support, including NLVVHC1G132DFT2G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NLVVHC1G132DFT2G requirements.
6.How does Aetrix verify that NLVVHC1G132DFT2G is sourced from the original manufacturer or authorized distributors?
All NLVVHC1G132DFT2G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NLVVHC1G132DFT2G meets industry standards.
7.What is the process for return or replacement of NLVVHC1G132DFT2G?
All NLVVHC1G132DFT2G units undergo pre-shipment inspection (PSI). If there is an issue with NLVVHC1G132DFT2G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NLVVHC1G132DFT2G part is unused and in its original packaging.
Return procedure for NLVVHC1G132DFT2G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NLVVHC1G132DFT2G Tags
-
SN74LVC1G14DBVR
Texas Instruments
-
SN74LVC1G14DCKR
Texas Instruments
-
SN74AHC1G14DBVR
Texas Instruments
-
SN74LVC1G08DBVR
Texas Instruments
-
SN74LVC1G08DCKR
Texas Instruments
-
SN74LVC1G32DCKR
Texas Instruments
-
SN74LVC1G04DBVR
Texas Instruments
.jpg)
-
74LVC1G08GW,125
Nexperia USA Inc.
-
SN74LVC1G04DCKR
Texas Instruments
-
SN74AHC1G08DBVR
Texas Instruments
-
SN74LVC1G32DBVR
Texas Instruments
-
SN74AHCT1G08DBVR
Texas Instruments
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

