onsemi NLVVHC1G14DTT1G
- Part No.:
- NLVVHC1G14DTT1G
- Manufacturer:
- onsemi
- Category:
- Gates and Inverters
- Package:
- SOT-23-5 Thin, TSOT-23-5
- Datasheet:
-
NLVVHC1G14DTT1G.pdf
- Description:
- IC INVERT SCHMITT 1CH 1INP 5TSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
NLVVHC1G14DTT1G from onsemi is a single Schmitt-trigger inverter IC designed for signal conditioning and noise-immune digital logic inversion in low-voltage systems. It operates from 2.0 V to 5.5 V, delivers 4.0 ns typical propagation delay at 5 V, features CMOS-level input thresholds (VT+ = 2.2–3.85 V, VT− = 0.9–1.65 V), and supports 5.5 V overvoltage-tolerant I/O for mixed-supply interfacing - used in industrial sensor signal cleanup and microcontroller input debouncing.
For engineers reviewing the NLVVHC1G14DTT1G datasheet, pinout, applications, or equivalent options, key selection considerations include its Schmitt-trigger hysteresis (0.3–1.6 V), IOFF partial power-down protection, ±8 mA drive capability at 3.0 V, SC-74A (SOT-25) 5-pin package, and AEC-Q100 qualification for automotive-grade reliability.
Technical Context
The NLVVHC1G14DTT1G implements a three-stage buffered output architecture that enhances noise immunity and ensures stable switching under noisy conditions. Its input structure tolerates up to 5.5 V regardless of VCC, enabling safe 5 V-to-3 V level translation without external components.
It integrates IOFF circuitry that disables I/O leakage when VCC = 0 V, preventing back-powering in partial power-down modes. The device exhibits defined hysteresis (VH = 0.3–1.6 V) with CMOS-compatible thresholds, distinguishing it from TTL-threshold variants like MC74VHC1GT14.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 2.0 V to 5.5 V - supports wide-input rail operation across battery-powered and industrial 3.3 V/5 V systems. |
| tPD (Typ) | 4.0 ns at VCC = 5 V, CL = 15 pF - enables high-speed signal inversion in timing-critical edge-detection paths. |
| Input Thresholds | VT+ = 2.2–3.85 V, VT− = 0.9–1.65 V (CMOS-level) - provides robust noise margin (>0.3 V) for slow-rising signals like mechanical switch inputs. |
| I/O Overvoltage | Up to 5.5 V independent of VCC - allows direct connection to 5 V buses while powered from 3.3 V, eliminating level-shifters. |
| IOFF Protection | Active when VCC = 0 V - prevents current backflow into powered subsystems during hot-swap or partial shutdown. |
| Output Drive | ±8 mA at VCC = 3.0 V - sufficient to directly drive multiple standard CMOS inputs or small LEDs without buffering. |
| Operating Temp | −55 °C to +125 °C - qualified for extended industrial and automotive under-hood environments. |
Pinout & Package
Package: SC-74A (SOT-25), 5-pin, 3.0 mm × 1.5 mm × 0.95 mm body, 0.95 mm pitch, Pb-free, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - A | Input | Inverting logic input with Schmitt-trigger hysteresis; accepts 0–5.5 V regardless of VCC. |
| 2 - GND | Ground Reference | Primary return path for supply and signal currents; must be low-impedance for noise immunity. |
| 3 - NC | No Connect | Internally unconnected; must remain floating or tied to GND per layout best practices. |
| 4 - Y | Output | Inverted, buffered output with ±8 mA drive; overvoltage tolerant up to 5.5 V even at VCC = 0 V. |
| 5 - VCC | Supply Voltage | Positive supply rail (2.0–5.5 V); powers internal logic and enables IOFF behavior when at 0 V. |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger input with programmable hysteresis | Hysteresis voltage (VH) ranges from 0.3 V (2.0 V VCC) to 1.6 V (5.5 V VCC), rejecting noise on slow or noisy signals. |
| Overvoltage-tolerant I/O | Inputs and outputs withstand 5.5 V regardless of VCC value - enables seamless 5 V ↔ 3.3 V interface without external clamps. |
| IOFF partial power-down protection | Blocks current flow between I/O pins when VCC = 0 V - critical for system-level power sequencing and hot-plug safety. |
| High noise immunity via buffered output | Three-stage internal buffer isolates output from input transients, minimizing crosstalk and improving signal integrity. |
| AEC-Q100 Grade 1 qualification | Qualified for automotive applications (−40 °C to +125 °C ambient), including engine control and body electronics modules. |
Applications
| Industrial Sensor Interface | Automotive Door Module |
|---|---|
|
Use Scenario: Cleaning noisy analog-to-digital converter (ADC) reference enable signals or mechanical switch bounce in PLC I/O modules. IC Role / Device Role / Timing Role: Signal conditioner and digital inverter that converts slow-rising, noisy switch closures into clean, jitter-free logic edges for microcontroller GPIO capture. Use Value: Eliminates need for external RC filters or software debouncing, reducing BOM count and firmware complexity while maintaining deterministic response time. |
Use Scenario: Debouncing door lock/unlock switch inputs in automotive body control modules (BCM) operating across −40 °C to +125 °C. IC Role / Device Role / Timing Role: Schmitt-trigger inverter providing hysteresis-based noise rejection on mechanical switch lines before MCU interrupt inputs. Use Value: Ensures reliable switch detection despite EMI from motors, solenoids, and RF sources - validated per AEC-Q100 Grade 1 requirements. |
| USB-C Power Delivery Sequencing | Medical Patient Monitor Front Panel |
|
Use Scenario: Inverting and cleaning USB-C CC line status signals during power role negotiation between source and sink devices. IC Role / Device Role / Timing Role: Level-shifting inverter translating 5 V CC line states to 3.3 V MCU logic while suppressing coupling noise from high-current power switches. Use Value: Prevents false CC state transitions caused by ground bounce or cable-induced transients, ensuring robust PD contract establishment. |
Use Scenario: Conditioning tactile button inputs on clinical-grade patient monitors where ESD and electromagnetic interference must not trigger false alarms. IC Role / Device Role / Timing Role: Input buffer with hysteresis converting mechanical button actuation into glitch-free interrupt signals for ARM Cortex-M4 host processor. Use Value: Meets IEC 60601-1 ESD immunity requirements (±8 kV contact, ±15 kV air) due to inherent 5.5 V I/O tolerance and robust input structure. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Schmitt-trigger inverter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MC74VHC1G14DFT2G | Same die, SC-88A (SOT-353) package - 2.1 mm × 1.25 mm, 0.65 mm pitch; slightly higher thermal resistance (377 °C/W vs. 320 °C/W). | Preferred for ultra-dense PCB layouts where footprint area is more constrained than height; less suitable for high-power-density thermal environments. | Select when board space is premium and thermal load is light; verify solder paste volume and reflow profile for smaller pad geometry. |
| SN74LVC1G14DBVR | Texas Instruments part; identical function but TTL-compatible thresholds (VT+ ≈ 1.7 V, VT− ≈ 0.5 V); 3.0 ns tPD at 3.3 V; different pinout (A/Y/VCC/GND/NC). | Better suited for legacy 3.3 V systems with marginal input rise times; lacks AEC-Q100 qualification and 5.5 V overvoltage tolerance. | Choose only for cost-sensitive non-automotive designs requiring faster propagation; avoid where 5 V interfacing or automotive qualification is required. |
Compared with MC74VHC1G14DFT2G, NLVVHC1G14DTT1G offers lower thermal resistance and automotive qualification in SC-74A; versus SN74LVC1G14DBVR, it provides wider voltage tolerance and guaranteed hysteresis stability across temperature, at the cost of slightly longer propagation delay.
Availability
NLVVHC1G14DTT1G is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive body electronics, and medical front-panel controls requiring stable component supply, long-term lifecycle support, and AEC-Q100 compliance.
Supply support for NLVVHC1G14DTT1G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (Nasdaq: ON) is a global semiconductor supplier delivering energy-efficient, intelligent power and sensing solutions for automotive, industrial, cloud, medical, and IoT applications.
The NLVVHC1G14DTT1G belongs to onsemi's VHC logic family - engineered for low-power, high-noise-immunity digital signal conditioning in harsh environments, with emphasis on automotive-grade reliability and mixed-voltage interoperability.
FAQ
What is the input hysteresis voltage range for NLVVHC1G14DTT1G across its full operating voltage?
The NLVVHC1G14DTT1G exhibits a hysteresis voltage (VH) ranging from 0.30 V at VCC = 2.0 V to 1.60 V at VCC = 5.5 V, measured across −55 °C to +125 °C. This hysteresis is intrinsic to its Schmitt-trigger design and ensures consistent noise rejection regardless of supply voltage or temperature - a key specification confirmed in the DC Electrical Characteristics table of the official onsemi datasheet (Rev. 30, Jan 2026).
Does NLVVHC1G14DTT1G support 5 V input signals while powered from 3.3 V?
Yes, NLVVHC1G14DTT1G supports 5 V input signals while powered from 3.3 V. Its inputs are overvoltage tolerant up to 5.5 V independent of VCC, as verified in the Maximum Ratings and Recommended Operating Conditions sections of the datasheet. This eliminates the need for external level-shifting components when interfacing 5 V sensors or legacy logic to 3.3 V microcontrollers.
Is NLVVHC1G14DTT1G pin-compatible with SN74LVC1G14?
No, NLVVHC1G14DTT1G is not pin-compatible with SN74LVC1G14. While both are single Schmitt-trigger inverters, NLVVHC1G14DTT1G uses SC-74A (SOT-25) pinout: Pin 1 = A, Pin 2 = GND, Pin 3 = NC, Pin 4 = Y, Pin 5 = VCC. SN74LVC1G14DBVR uses SOT-23-5: Pin 1 = A, Pin 2 = GND, Pin 3 = Y, Pin 4 = VCC, Pin 5 = NC - a different terminal assignment confirmed in TI's SLRS208F datasheet.
What is the maximum output drive strength of NLVVHC1G14DTT1G at 3.0 V supply?
At VCC = 3.0 V, NLVVHC1G14DTT1G delivers ±8 mA output drive strength (IOL/IOH), as specified in the DC Electrical Characteristics table for the MC74VHC1G14 variant. This is sufficient to drive 10 standard CMOS loads (1 TTL unit load = 0.8 mA) or directly interface with small indicator LEDs using appropriate current-limiting resistors.
Does NLVVHC1G14DTT1G include IOFF functionality, and how does it behave during power-down?
Yes, NLVVHC1G14DTT1G includes IOFF functionality. When VCC = 0 V, the IOFF circuit actively disables I/O paths, limiting input/output leakage current to ≤10 µA (max) - verified in the DC Electrical Characteristics table. This prevents back-powering of powered subsystems during partial power-down or hot-insertion scenarios, a critical feature for system-level power sequencing integrity.
NLVVHC1G14DTT1G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 74VHC
- Package/Case:
- SOT-23-5 Thin, TSOT-23-5
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Inverter
- Number of Circuits:
- 1
- Number of Inputs:
- 1
- Features:
- Schmitt Trigger
- Voltage - Supply:
- 2V ~ 5.5V
- Current - Quiescent (Max):
- 1 µA
- Current - Output High, Low:
- 8mA, 8mA
- Input Logic Level - Low:
- 0.9V ~ 1.65V
- Input Logic Level - High:
- 2.2V ~ 3.85V
- Max Propagation Delay @ V, Max CL:
- 10.6ns @ 5V, 50pF
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 5-TSOP
NLVVHC1G14DTT1G FAQ
1.How can I place an order for NLVVHC1G14DTT1G through Aetrix?
Please submit a Request for Quotation (RFQ) for NLVVHC1G14DTT1G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NLVVHC1G14DTT1G reliable?
The price and inventory of NLVVHC1G14DTT1G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NLVVHC1G14DTT1G is usually 5 days.
3.What payment methods are accepted for NLVVHC1G14DTT1G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NLVVHC1G14DTT1G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NLVVHC1G14DTT1G?
NLVVHC1G14DTT1G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NLVVHC1G14DTT1G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NLVVHC1G14DTT1G?
For technical support, including NLVVHC1G14DTT1G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NLVVHC1G14DTT1G requirements.
6.How does Aetrix verify that NLVVHC1G14DTT1G is sourced from the original manufacturer or authorized distributors?
All NLVVHC1G14DTT1G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NLVVHC1G14DTT1G meets industry standards.
7.What is the process for return or replacement of NLVVHC1G14DTT1G?
All NLVVHC1G14DTT1G units undergo pre-shipment inspection (PSI). If there is an issue with NLVVHC1G14DTT1G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NLVVHC1G14DTT1G part is unused and in its original packaging.
Return procedure for NLVVHC1G14DTT1G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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