onsemi NLVVHC86DTR2G
- Part No.:
- NLVVHC86DTR2G
- Manufacturer:
- onsemi
- Category:
- Gates and Inverters
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
NLVVHC86DTR2G.pdf
- Description:
- IC GATE XOR 4CH 2-INP 14TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
NLVVHC86DTR2G from onsemi is a quad 2-input XOR gate IC in TSSOP-14 package, operating from 2.0 V to 5.5 V, delivering 4.8 ns typical propagation delay at 5 V and full 5.0 V CMOS-level output swing. It features TTL-compatible inputs only in the VHCT variant - this part is the VHC family version with standard CMOS input thresholds. It is used in digital logic interfacing, parity generation, and waveform shaping in industrial control and communication subsystems.
For engineers reviewing the NLVVHC86DTR2G datasheet, pinout, applications, or equivalent options, key selection considerations include its 2–5.5 V supply range, 4.8 ns (typ) tPD at 5 V, CMOS input compatibility, 5.5 V tolerant inputs, and automotive-grade qualification per AEC-Q100 for reliability-critical designs.
Technical Context
The NLVVHC86DTR2G implements four independent 2-input exclusive-OR logic gates using silicon-gate CMOS technology. Its three-stage internal architecture includes buffered outputs for high noise immunity and stable switching behavior. Input structures tolerate up to 5.5 V regardless of VCC, enabling safe 5 V-to-3 V system interfacing without level shifters.
It operates across −55 °C to +125 °C with guaranteed performance under 2.0–5.5 V supply. The device exhibits balanced tPLH/tPHL delays, low dynamic noise (VOLP ≤ 0.8 V), and latchup immunity exceeding 100 mA per JEDEC JESD78 Class II.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 2.0 V to 5.5 V - supports mixed-voltage system integration including 3.3 V and 5 V domains. |
| tPD (Typ) | 4.8 ns at VCC = 5.0 V, CL = 15 pF - enables high-speed combinational logic in timing-critical paths. |
| Input Voltage Tolerance | −0.5 V to +5.5 V - allows hot-plug and bus-sharing with higher-voltage peripherals without damage. |
| VIH/VIL | VIH = 0.7×VCC, VIL = 0.3×VCC - CMOS-compatible thresholds ensure clean logic recognition across supply range. |
| Output Drive | ±8 mA at VCC = 4.5 V - sufficient to drive multiple standard CMOS loads or one TTL input. |
| Quiescent ICC | 2.0 µA max at 25 °C - ultra-low static power ideal for battery-backed or always-on logic functions. |
| ESD Rating | HBM > 2000 V - robust handling during board assembly and field service without special ESD precautions. |
Pinout & Package
TSSOP-14 package (Case 948G), 4.9 mm × 4.4 mm × 1.2 mm body, 0.65 mm pitch, Pb-free and RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | A1 | First input of Gate 1 - accepts standard CMOS logic levels; tolerant to 5.5 V. |
| 2 | B1 | Second input of Gate 1 - identical electrical characteristics to Pin 1. |
| 3 | Y1 | Output of Gate 1 - provides rail-to-rail CMOS swing (0 V to VCC) with ±8 mA drive capability. |
| 4 | A2 | First input of Gate 2 - electrically isolated; shares same input structure as Pins 1 and 2. |
| 5 | B2 | Second input of Gate 2 - no internal connection to other gates; fully independent. |
| 6 | Y2 | Output of Gate 2 - matches Y1 in voltage range, drive strength, and noise immunity. |
| 7 | GND | Ground reference - must be connected to system common; serves all four gates. |
| 8 | Y3 | Output of Gate 3 - identical AC/DC specs to Y1/Y2; no shared loading effects. |
| 9 | A3 | First input of Gate 3 - pin-compatible with A1/A2; no crosstalk between gates. |
| 10 | B3 | Second input of Gate 3 - supports same VIH/VIL thresholds and input leakage (<±1.0 µA). |
| 11 | Y4 | Output of Gate 4 - final gate output; maintains 4.8 ns tPD consistency across temperature. |
| 12 | A4 | First input of Gate 4 - connects directly to internal CMOS inverter pair; no pull-up/down required. |
| 13 | B4 | Second input of Gate 4 - unused inputs must be tied to VCC or GND to prevent floating states. |
| 14 | VCC | Positive supply - decoupling capacitor (0.1 µF ceramic) recommended within 5 mm of this pin. |
Key Features
| Feature | Design Value |
|---|---|
| High-speed XOR operation | 4.8 ns typical propagation delay at 5 V enables use in clock-domain crossing and real-time parity checking. |
| Wide supply voltage range | 2.0 V to 5.5 V operation supports direct integration into both legacy 5 V and modern low-voltage embedded systems. |
| 5.5 V-tolerant inputs | Allows safe interface between 5 V sensors/microcontrollers and 3.3 V logic without external level translators. |
| High noise immunity | VNIH = VNIL = 28% VCC ensures reliable switching in electrically noisy industrial environments. |
| Automotive qualification | AEC-Q100 Grade 1 qualified (−40 °C to +125 °C) with PPAP capability - suitable for engine control and ADAS subsystems. |
Applications
| Parity Generator / Checker | Digital Signal Routing |
|---|---|
|
Use Scenario: Generating or verifying odd/even parity bits in UART, SPI, or memory data paths to detect single-bit transmission errors. IC Role / Device Role / Timing Role: Performs bitwise XOR across parallel data lines; each gate handles one bit pair with sub-5 ns latency. Use Value: Enables real-time error detection with zero additional timing overhead due to deterministic 4.8 ns propagation delay. |
Use Scenario: Selecting between two digital signal sources (e.g., primary vs. backup sensor) using control-line XOR gating. IC Role / Device Role / Timing Role: Acts as a programmable signal combiner where output = A ⊕ B determines path enablement. Use Value: Eliminates need for dedicated multiplexers; leverages inherent logic function to reduce component count and PCB area. |
| Waveform Shaping | Industrial Control Logic |
|
Use Scenario: Converting square waves to pulse trains (e.g., edge detection in encoder signals or PWM timing circuits). IC Role / Device Role / Timing Role: Configured as an XOR-based differentiator: Y = A ⊕ (A delayed by RC network). Use Value: Achieves precise, supply-independent pulse width control using only passive components and one gate. |
Use Scenario: Implementing safety interlocks in PLC I/O modules where dual-channel agreement is verified via XOR comparison. IC Role / Device Role / Timing Role: Compares redundant sensor outputs; mismatch (Y = HIGH) triggers fault shutdown. Use Value: Provides SIL-2-capable diagnostic coverage using discrete logic with known failure modes and AEC-Q100 reliability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar XOR gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MC74VHCT86ADTR2G | TTL-compatible inputs (VIH = 2.0 V min at 5 V), otherwise identical AC/DC specs and pinout. | Required when driving from legacy 5 V TTL or LVTTL sources; not needed for pure CMOS systems. | Select MC74VHCT86ADTR2G only if upstream logic uses TTL voltage thresholds; otherwise NLVVHC86DTR2G is preferred for lower input current and wider VCC flexibility. |
| SN74LVC86APW | Lower VCC min (1.65 V), higher speed (3.9 ns typ), but rated only to 85 °C ambient and not AEC-Q100 qualified. | Suitable for commercial portable electronics; unsuitable for under-hood automotive or extended-temperature industrial use. | Choose SN74LVC86APW for cost-sensitive consumer designs needing faster timing; retain NLVVHC86DTR2G for automotive, aerospace, or high-reliability industrial deployments. |
Compared with MC74VHCT86ADTR2G, NLVVHC86DTR2G offers superior input voltage flexibility and lower static power, while SN74LVC86APW trades automotive qualification and temperature range for higher speed and lower minimum supply - making NLVVHC86DTR2G the optimal choice for thermally demanding, safety-conscious applications.
Availability
NLVVHC86DTR2G is available at Aetrix Electronics and suitable for industrial automation, automotive body electronics, and communications infrastructure requiring stable component supply, long-term lifecycle support, and AEC-Q100 compliance.
Supply support for NLVVHC86DTR2G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient, high-performance silicon solutions for automotive, industrial, cloud, and IoT applications.
The NLVVHC86DTR2G belongs to the VHC logic family, designed for high-speed, low-power CMOS-compatible digital interfacing in harsh-environment systems where reliability and wide supply tolerance are critical.
FAQ
What is the maximum operating temperature range for NLVVHC86DTR2G?
The NLVVHC86DTR2G is specified for operation from −55 °C to +125 °C, meeting AEC-Q100 Grade 1 requirements. This extended range supports deployment in engine compartments, industrial motor drives, and outdoor telecom equipment where ambient temperatures exceed standard commercial limits. All DC and AC parameters in the datasheet are guaranteed across this full range.
Is NLVVHC86DTR2G pin-compatible with older 74HC86 devices?
Yes, NLVVHC86DTR2G is pin- and function-compatible with industry-standard 74HC86 and 74HCT86 devices in TSSOP-14 packaging. Its pinout matches Figure 2 in the datasheet exactly: 14-pin layout with GND at Pin 7 and VCC at Pin 14. No PCB redesign is needed when upgrading from HC/HCT variants, though VCC range and input thresholds differ slightly.
Does NLVVHC86DTR2G support 3.3 V-only operation?
Yes, NLVVHC86DTR2G operates fully across 2.0 V to 5.5 V, including stable 3.3 V operation. At VCC = 3.3 V, it delivers 7.0 ns typical propagation delay (CL = 15 pF), maintains CMOS input thresholds (VIH = 2.31 V, VIL = 0.99 V), and provides rail-to-rail 3.3 V outputs capable of driving eight 74LVC inputs. No level-shifting circuitry is required.
What is the purpose of the "NLV" prefix in NLVVHC86DTR2G?
The "NLV" prefix denotes onsemi's Automotive and Industrial Enhanced Reliability product line. NLVVHC86DTR2G undergoes additional screening, extended temperature testing, and AEC-Q100 qualification - distinguishing it from standard VHC86 parts. It guarantees PPAP readiness, lot traceability, and enhanced moisture sensitivity level (MSL1), making it suitable for safety-critical automotive ECUs and industrial control units.
Can unused inputs on NLVVHC86DTR2G be left floating?
No, unused inputs on NLVVHC86DTR2G must never be left floating. Per datasheet Section 3 (Recommended Operating Conditions), all unused inputs must be tied to a valid logic level - either VCC or GND - using a pull-up or pull-down resistor (1–10 kΩ typical). Floating inputs cause increased ICC, unpredictable output states, and potential device malfunction due to internal MOSFET threshold uncertainty.
NLVVHC86DTR2G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 74VHC
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- XOR (Exclusive OR)
- Number of Circuits:
- 4
- Number of Inputs:
- 2
- Features:
- -
- Voltage - Supply:
- 2V ~ 5.5V
- Current - Quiescent (Max):
- 2 µA
- Current - Output High, Low:
- 8mA, 8mA
- Input Logic Level - Low:
- -
- Input Logic Level - High:
- -
- Max Propagation Delay @ V, Max CL:
- 8.8ns @ 5V, 50pF
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-TSSOP
NLVVHC86DTR2G FAQ
1.How can I place an order for NLVVHC86DTR2G through Aetrix?
Please submit a Request for Quotation (RFQ) for NLVVHC86DTR2G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NLVVHC86DTR2G reliable?
The price and inventory of NLVVHC86DTR2G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NLVVHC86DTR2G is usually 5 days.
3.What payment methods are accepted for NLVVHC86DTR2G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NLVVHC86DTR2G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NLVVHC86DTR2G?
NLVVHC86DTR2G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NLVVHC86DTR2G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NLVVHC86DTR2G?
For technical support, including NLVVHC86DTR2G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NLVVHC86DTR2G requirements.
6.How does Aetrix verify that NLVVHC86DTR2G is sourced from the original manufacturer or authorized distributors?
All NLVVHC86DTR2G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NLVVHC86DTR2G meets industry standards.
7.What is the process for return or replacement of NLVVHC86DTR2G?
All NLVVHC86DTR2G units undergo pre-shipment inspection (PSI). If there is an issue with NLVVHC86DTR2G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NLVVHC86DTR2G part is unused and in its original packaging.
Return procedure for NLVVHC86DTR2G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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