onsemi NLVVHCT125ADTRG
- Part No.:
- NLVVHCT125ADTRG
- Manufacturer:
- onsemi
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
NLVVHCT125ADTRG.pdf
- Description:
- IC BUF NON-INVERT 5.5V 14TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
NLVVHCT125ADTRG from onsemi is an automotive-grade quad bus buffer with 3-state control inputs, fabricated in silicon gate CMOS technology. It delivers TTL-compatible input thresholds (VIL = 0.8 V, VIH = 2.0 V), 3.8 ns typical propagation delay at 5.0 V, full 5.0 V CMOS output swing, and operates across 2.0–5.5 V supply range. It serves as a level-shifting interface between 3.3 V and 5.0 V systems in engine control units and body electronics.
For engineers reviewing the NLVVHCT125ADTRG datasheet, pinout, applications, or equivalent options, key selection criteria include its AEC-Q100 qualification, TSSOP-14 package, 3-state enable logic (active-low OE), ±8 mA drive capability, and input tolerance up to 7.0 V - critical for hot-swap and mixed-voltage automotive signal routing.
Technical Context
The NLVVHCT125ADTRG implements four independent non-inverting buffers, each with a dedicated active-low 3-state enable (OE) input. Its input structure tolerates voltages from −0.5 V to +7.0 V regardless of VCC, enabling robust interfacing between 3.0 V and 5.0 V domains without external level shifters.
Internally, it uses three-stage buffering to ensure high noise immunity and balanced propagation delays. The output stage provides controlled rise/fall times and supports hot insertion via power-down protection - outputs remain safe even when VCC = 0 V, and inputs are protected against supply–input mismatch during battery backup or system wake-up events.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 2.0 V to 5.5 V - enables operation in both 3.3 V and 5.0 V automotive subsystems without voltage translation. |
| Propagation Delay (tPD) | 3.8 ns (typ) at VCC = 5.0 V, CL = 15 pF - supports high-speed data routing in CAN/LIN gateway interfaces. |
| Output Drive Strength | ±8.0 mA at VCC = 4.5 V - sufficient to drive multiple TTL loads or 50 pF traces in distributed ECUs. |
| Input Voltage Tolerance | −0.5 V to +7.0 V - prevents damage during load dump transients or cross-supply probing in vehicle harness testing. |
| Quiescent Supply Current | 4.0 µA (max) at TA = 25°C - ensures low static power in always-on vehicle modules like door controllers. |
| ESD Rating | HBM > 2000 V, MM > 200 V - meets baseline requirements for assembly handling and in-vehicle ESD robustness. |
| Operating Temperature | −55°C to +125°C - qualified for under-hood and transmission control applications per AEC-Q100 Grade 1. |
Pinout & Package
TSSOP-14 (DT suffix, Case 948G), Pb-free, RoHS compliant, 4.4 mm × 5.0 mm footprint with 0.65 mm pitch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 10, 13 | Data Input (A1–A4) | Non-inverting buffer inputs; accept TTL- or CMOS-level signals; tolerate up to 7.0 V. |
| 2, 5, 11, 14 | 3-State Enable (OE1–OE4) | Active-low controls; OE = HIGH forces output into high-impedance state - essential for bus arbitration. |
| 3, 6, 8, 12 | Buffer Output (Y1–Y4) | CMOS-compatible outputs with rail-to-rail swing; drive capability ±8 mA; support hot insertion. |
| 7 | GND | Ground reference for all I/O and internal logic; must be low-impedance connection in automotive PCB layout. |
| 14 | VCC | Primary power supply pin; decoupling capacitor (100 nF) required within 5 mm for noise suppression. |
Key Features
| Feature | Design Value |
|---|---|
| TTL-Compatible Inputs | VIL = 0.8 V / VIH = 2.0 V - allows direct connection to legacy 5 V microcontrollers without pull-ups or translators. |
| Wide Supply Range | 2.0 V to 5.5 V operation - supports dual-rail designs and brown-out resilience in 12 V vehicle electrical systems. |
| Input/Output Protection | Inputs withstand −0.5 V to +7.0 V; outputs safe at VCC = 0 V - eliminates need for external clamping diodes in body control modules. |
| AEC-Q100 Qualified | NLV prefix indicates automotive qualification, PPAP capability, and unique site/control change tracking - required for Tier 1 production release. |
| Low Dynamic Noise | VOLP ≤ 0.8 V (max) - minimizes ground bounce in multi-buffer fanout configurations on shared PCB planes. |
Applications
| Engine Control Unit (ECU) Signal Conditioning | Body Control Module (BCM) Bus Isolation |
|---|---|
Use Scenario: Routing sensor data (e.g., throttle position, knock sensor) between 3.3 V MCU and 5.0 V analog front-end or legacy actuator drivers. IC Role / Device Role / Timing Role: Level-shifting quad buffer with independent 3-state control per channel - enables time-multiplexed access to shared diagnostic lines. Use Value: Eliminates discrete level translators; 3.8 ns tPD preserves timing margins in closed-loop fuel injection timing windows. | Use Scenario: Isolating LIN bus transceiver I/O from 3.3 V microcontroller GPIO during sleep mode to prevent current leakage. IC Role / Device Role / Timing Role: Quad 3-state buffer with OE-controlled high-Z outputs - allows MCU to disconnect peripherals while maintaining bus integrity. Use Value: Reduces standby current by >95% vs. always-connected drivers; input tolerance prevents latch-up during battery voltage sag. |
| Instrument Cluster Display Interface | Transmission Control Unit (TCU) Diagnostic Port |
Use Scenario: Driving multiple 5.0 V display segment drivers from a 3.3 V graphics controller in digital dashboards. IC Role / Device Role / Timing Role: Non-inverting voltage-level translator with rail-to-rail output swing - ensures full brightness and contrast across all segments. Use Value: Full 5.0 V output swing guarantees reliable turn-on of LED drivers; ±8 mA drive supports parallel segment loading. | Use Scenario: Enabling/disabling OBD-II diagnostic communication paths between 5.0 V CAN transceivers and 3.3 V diagnostic processors. IC Role / Device Role / Timing Role: Quad buffer with independent OE pins - permits selective activation of J1939 or ISO 15765 channels without software reconfiguration. Use Value: Enables hardware-based diagnostic port partitioning; AEC-Q100 qualification ensures reliability over 15-year vehicle lifetime. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad bus buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MC74VHCT125ADTRG | Same die, non-automotive grade; lacks NLV prefix, AEC-Q100 qualification, and PPAP documentation. | Approved for industrial/commercial use only; not accepted in OEM automotive BOMs requiring PPAP submission. | Select when cost sensitivity outweighs automotive compliance requirements and temperature range ≤ 85°C suffices. |
| SN74LVC125APW | 3.3 V only (1.65–3.6 V); lower drive (±24 mA); no 7.0 V input tolerance; different pinout (SOIC-14 vs TSSOP-14). | Suitable for 3.3 V-only systems; requires redesign if interfacing to 5 V buses or surviving load dump events. | Choose for new 3.3 V designs where board space allows SOIC-14 and automotive qualification is unnecessary. |
Compared with MC74VHCT125ADTRG, NLVVHCT125ADTRG adds AEC-Q100 Grade 1 validation and traceable automotive change control, while SN74LVC125APW offers higher drive but sacrifices mixed-voltage interoperability and automotive qualification - making NLVVHCT125ADTRG the sole drop-in solution for legacy 5 V automotive signal routing upgrades.
Availability
NLVVHCT125ADTRG is available at Aetrix Electronics and suitable for engine control units, body control modules, and instrument cluster interfaces requiring stable component supply across extended temperature ranges and automotive lifecycle commitments.
Supply support for NLVVHCT125ADTRG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier focused on energy-efficient electronics for automotive, industrial, cloud, medical, and IoT applications.
The VHCT logic family - including NLVVHCT125ADTRG - was designed specifically for mixed-voltage automotive signal routing, combining TTL compatibility, wide VCC range, and AEC-Q100 reliability to replace legacy bipolar buffers in ECU and BCM designs.
FAQ
What is the operating temperature range for NLVVHCT125ADTRG?
The NLVVHCT125ADTRG is rated for −55°C to +125°C operation and is AEC-Q100 qualified for automotive Grade 1 applications. This range covers under-hood environments such as engine control units and transmission control modules. The device maintains specified DC and AC performance across this full range, with derating applied above 65°C per the TSSOP package thermal limits. NLVVHCT125ADTRG's design ensures stable timing and logic integrity even during rapid thermal cycling in vehicle start-stop cycles.
Is NLVVHCT125ADTRG pin-compatible with standard 74-series logic devices?
Yes, NLVVHCT125ADTRG is pin- and function-compatible with industry-standard 74HCT125 and 74VHCT125 devices in TSSOP-14 packages. Its pinout matches the JEDEC MS-012 standard: inputs (A1–A4) and enables (OE1–OE4) occupy alternating positions, with outputs (Y1–Y4), VCC, and GND placed identically. This allows direct replacement in existing layouts without PCB revision - provided the original design used TSSOP-14 and accounted for the NLV prefix's automotive qualification requirements.
Does NLVVHCT125ADTRG support hot insertion?
Yes, NLVVHCT125ADTRG supports hot insertion due to its powered-off output protection: outputs remain safe even when VCC = 0 V, and inputs tolerate −0.5 V to +7.0 V regardless of supply state. This behavior is confirmed in the datasheet's "Power Down Protection" feature and Maximum Ratings table. In practice, NLVVHCT125ADTRG can be safely inserted into a live 5 V backplane or module connector without damaging itself or upstream circuitry - a key requirement for serviceable automotive subassemblies like infotainment head units or ADAS camera modules.
What is the maximum output drive capability of NLVVHCT125ADTRG?
NLVVHCT125ADTRG delivers ±8.0 mA output drive per channel at VCC = 4.5 V, as specified in the DC Electrical Characteristics table under VOL and VOH test conditions. This enables driving multiple TTL loads (e.g., 10x 74HCT inputs) or 50 pF transmission lines typical in automotive wiring harnesses. The device maintains this drive strength across −55°C to +125°C, with VOL ≤ 0.52 V and VOH ≥ 2.34 V under worst-case conditions - ensuring noise margin preservation in electrically noisy vehicle environments.
How does NLVVHCT125ADTRG handle voltage level translation between 3.3 V and 5.0 V systems?
NLVVHCT125ADTRG performs bidirectional level translation via its TTL-compatible inputs and full 5.0 V CMOS output swing. Inputs recognize 3.3 V logic highs (VIH = 2.0 V min) and provide rail-to-rail 5.0 V outputs, enabling 3.3 V MCUs to drive 5.0 V peripherals. Its input tolerance up to 7.0 V also allows reverse-direction interfacing - e.g., 5.0 V sensors feeding 3.3 V processors - without external components. This capability is explicitly documented in the datasheet's "level converter" application note and verified across recommended operating conditions.
NLVVHCT125ADTRG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- -
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 2V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-TSSOP
NLVVHCT125ADTRG FAQ
1.How can I place an order for NLVVHCT125ADTRG through Aetrix?
Please submit a Request for Quotation (RFQ) for NLVVHCT125ADTRG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NLVVHCT125ADTRG reliable?
The price and inventory of NLVVHCT125ADTRG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NLVVHCT125ADTRG is usually 5 days.
3.What payment methods are accepted for NLVVHCT125ADTRG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NLVVHCT125ADTRG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NLVVHCT125ADTRG?
NLVVHCT125ADTRG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NLVVHCT125ADTRG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NLVVHCT125ADTRG?
For technical support, including NLVVHCT125ADTRG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NLVVHCT125ADTRG requirements.
6.How does Aetrix verify that NLVVHCT125ADTRG is sourced from the original manufacturer or authorized distributors?
All NLVVHCT125ADTRG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NLVVHCT125ADTRG meets industry standards.
7.What is the process for return or replacement of NLVVHCT125ADTRG?
All NLVVHCT125ADTRG units undergo pre-shipment inspection (PSI). If there is an issue with NLVVHCT125ADTRG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NLVVHCT125ADTRG part is unused and in its original packaging.
Return procedure for NLVVHCT125ADTRG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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