My Inquiry
My Account
onsemi NLVVHCT126ADTR2G
- Part No.:
- NLVVHCT126ADTR2G
- Manufacturer:
- onsemi
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
NLVVHCT126ADTR2G.pdf
- Description:
- IC BUFF NON-INVERT 5.5V 14TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:2,330
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
NLVVHCT126ADTR2G from onsemi is a quad 3-state bus buffer with TTL-compatible inputs and CMOS-level outputs, designed for bidirectional voltage translation between 3.3 V and 5.0 V logic domains. It features 3.8 ns typical propagation delay at 5.0 V, ±25 mA output drive per channel, 4.0 µA max quiescent current, and operates across −55 °C to +125 °C - used in industrial control backplanes and automotive body electronics.
For engineers reviewing the NLVVHCT126ADTR2G datasheet, pinout, applications, or equivalent options, this page delivers verified electrical specs, TSSOP-14 package details, real-world interface use cases, and validated alternative parts for level-shifting and bus isolation designs.
Technical Context
The NLVVHCT126ADTR2G implements four independent non-inverting buffers, each with an active-high 3-state enable (OE) controlling output impedance. Its input structure tolerates up to 5.5 V, enabling safe interfacing of 5 V systems to 3 V logic without external clamping.
Internal circuitry includes three-stage buffering for high noise immunity (28% VCC), power-down protection on all inputs, and output structures that remain protected when VCC = 0 V - critical for hot-swap and battery-backup applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 2.0 V to 5.5 V - supports mixed-voltage system integration without level shifters |
| Propagation Delay (tPLH/tPHL) | 3.8 ns typ @ 5.0 V, CL = 15 pF - enables high-speed data transfer in 25 MHz+ bus systems |
| Output Drive Strength | ±8 mA @ VOL ≤ 0.52 V - sufficient to drive multiple CMOS loads or short PCB traces |
| Input Compatibility | TTL-level inputs (VIL ≤ 0.8 V, VIH ≥ 2.0 V @ 5.0 V) - directly interfaces legacy 5 V controllers |
| Operating Temperature | −55 °C to +125 °C - qualified for under-hood automotive and industrial environments |
| ESD Rating | Human Body Model > 2000 V - robust against handling damage during assembly |
| Quiescent Current | 2.0 µA max @ 25 °C - ultra-low static power for always-on subsystems |
Pinout & Package
TSSOP-14 (Case 948G), 4.9 mm × 4.4 mm × 1.2 mm body, 0.65 mm pitch, Pb-free, RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 10, 13 | Buffer Input (A1–A4) | Accepts TTL/CMOS logic signals; tolerant to 5.5 V regardless of VCC |
| 2, 5, 9, 12 | 3-State Enable (OE1–OE4) | Active-high control: OE = HIGH → output enabled; OE = LOW → high-impedance state |
| 3, 6, 8, 11 | Buffer Output (Y1–Y4) | Full-rail CMOS swing (0 V to VCC) with ±25 mA sink/source capability |
| 7 | GND | Ground reference for all I/O and internal logic; must be low-impedance connection |
| 14 | VCC | Primary supply (2.0–5.5 V); powers internal logic and drives output high levels |
Key Features
| Feature | Design Value |
|---|---|
| Hot-swap safe outputs | Output structures remain protected when VCC = 0 V - prevents latch-up during live insertion |
| Input overvoltage tolerance | Inputs withstand up to 5.5 V independent of VCC - eliminates need for external clamps in 5 V-to-3.3 V translation |
| High noise immunity | 28% VCC noise margin (VNIH/VNIL) - ensures reliable operation in electrically noisy engine compartments |
| Low dynamic power | 15 pF CPD - minimizes switching current in high-frequency clock/data buses |
| AEC-Q100 qualified | Automotive-grade reliability with PPAP support - suitable for body control modules and gateway ECUs |
Applications
| Automotive Body Control Module | Industrial PLC Backplane |
|---|---|
Use Scenario: Interfacing 5 V microcontroller GPIOs to 3.3 V CAN transceiver and sensor ADCs within a vehicle door module. IC Role / Device Role / Timing Role: Bidirectional level translator and bus isolator, enabling shared data lines between mixed-voltage peripherals. Use Value: Eliminates discrete resistor-divider networks while maintaining signal integrity and meeting AEC-Q100 temperature requirements. | Use Scenario: Isolating field I/O expansion slots from the main CPU bus in a modular programmable logic controller. IC Role / Device Role / Timing Role: Quad 3-state buffer providing controlled bus access and preventing contention during hot-swap of I/O cards. Use Value: Enables deterministic bus arbitration with sub-4 ns propagation delay and guaranteed high-impedance disable timing. |
| Medical Diagnostic Imaging Interface | Test Equipment Signal Routing |
Use Scenario: Level-shifting control signals between a 5 V FPGA configuration interface and 3.3 V image sensor array in portable ultrasound equipment. IC Role / Device Role / Timing Role: Non-inverting buffer with TTL-compatible input thresholds ensuring reliable FPGA boot sequence handshaking. Use Value: Guarantees setup/hold timing margins across −40 °C to +85 °C operating range without derating. | Use Scenario: Multiplexing multiple DUT (device-under-test) digital stimulus channels onto a single high-speed acquisition path in automated test systems. IC Role / Device Role / Timing Role: Quad gate with independent OE controls allowing precise time-gated signal routing without crosstalk. Use Value: Delivers <1.0 ns output-to-output skew (tOSLH) for synchronized multi-channel sampling. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MC74VHCT126ADR2G | SOIC-14 package; identical electrical specs and pinout | Larger footprint; better thermal dissipation but unsuitable for space-constrained PCBs | Select when board layout allows SOIC and higher power dissipation margin is needed |
| SN74LVC126APWR | 3.3 V only supply (1.65–3.6 V); LVTTL-compatible inputs; lower drive (±24 mA) | Not suitable for 5 V input interfacing; requires external level shifting for mixed-voltage use | Select only for pure 3.3 V systems where cost and size are prioritized over voltage flexibility |
Compared with MC74VHCT126ADR2G, NLVVHCT126ADTR2G offers identical functionality in a smaller TSSOP-14 package ideal for compact automotive modules; compared with SN74LVC126APWR, it uniquely supports direct 5 V input tolerance and full 5 V CMOS output swing - essential for legacy system upgrades.
Availability
NLVVHCT126ADTR2G is available at Aetrix Electronics and suitable for automotive body electronics, industrial PLC backplanes, medical imaging interfaces, and test equipment signal routing requiring stable component supply across extended temperature ranges.
Supply support for NLVVHCT126ADTR2G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier focused on energy-efficient electronics for automotive, industrial, cloud, and medical applications.
The NLVVHCT126ADTR2G belongs to the VHCT logic family, engineered specifically for seamless voltage translation and robust operation in harsh environments - targeting automotive infotainment, ADAS domain controllers, and industrial automation interfaces.
FAQ
What is the maximum input voltage rating for NLVVHCT126ADTR2G?
The NLVVHCT126ADTR2G supports DC input voltages up to 5.5 V on all pins, independent of VCC. This overvoltage tolerance allows safe interfacing with 5 V logic even when powered from 3.3 V, eliminating the need for external clamping diodes in mixed-voltage designs involving NLVVHCT126ADTR2G.
Does NLVVHCT126ADTR2G support hot-swap operation?
Yes, NLVVHCT126ADTR2G includes power-off protection on its output structures, enabling safe operation when VCC = 0 V. This feature prevents device destruction due to supply-input mismatches during hot insertion - a key requirement for modular NLVVHCT126ADTR2G-based backplane designs in industrial and automotive systems.
What is the output drive capability of NLVVHCT126ADTR2G at 3.3 V supply?
At VCC = 3.3 V, NLVVHCT126ADTR2G delivers ±4 mA output drive (IOL/IOH) with VOL ≤ 0.44 V and VOH ≥ 2.48 V. This meets standard LVTTL and 3.3 V CMOS load requirements, supporting fan-out to up to 10 standard CMOS inputs or driving 50 Ω transmission lines with minimal distortion in NLVVHCT126ADTR2G implementations.
Is NLVVHCT126ADTR2G qualified for automotive applications?
Yes, NLVVHCT126ADTR2G is AEC-Q100 qualified (Grade 1: −40 °C to +125 °C ambient) and PPAP capable. Its design includes enhanced ESD protection (>2000 V HBM), latch-up immunity (>100 mA), and extended temperature operation - making it suitable for body control units, gateway modules, and other non-safety-critical automotive electronics using NLVVHCT126ADTR2G.
How does the 3-state enable (OE) function in NLVVHCT126ADTR2G?
In NLVVHCT126ADTR2G, each of the four OE inputs (pins 2, 5, 9, 12) is active-high: when OE = HIGH, the corresponding Y output follows the A input; when OE = LOW, the Y output enters high-impedance state. This allows independent control of bus segments, preventing contention in multi-master systems - a core functional behavior defined for every NLVVHCT126ADTR2G channel.
NLVVHCT126ADTR2G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 74VHCT
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-TSSOP
NLVVHCT126ADTR2G FAQ
1.How can I place an order for NLVVHCT126ADTR2G through Aetrix?
Please submit a Request for Quotation (RFQ) for NLVVHCT126ADTR2G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NLVVHCT126ADTR2G reliable?
The price and inventory of NLVVHCT126ADTR2G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NLVVHCT126ADTR2G is usually 5 days.
3.What payment methods are accepted for NLVVHCT126ADTR2G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NLVVHCT126ADTR2G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NLVVHCT126ADTR2G?
NLVVHCT126ADTR2G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NLVVHCT126ADTR2G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NLVVHCT126ADTR2G?
For technical support, including NLVVHCT126ADTR2G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NLVVHCT126ADTR2G requirements.
6.How does Aetrix verify that NLVVHCT126ADTR2G is sourced from the original manufacturer or authorized distributors?
All NLVVHCT126ADTR2G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NLVVHCT126ADTR2G meets industry standards.
7.What is the process for return or replacement of NLVVHCT126ADTR2G?
All NLVVHCT126ADTR2G units undergo pre-shipment inspection (PSI). If there is an issue with NLVVHCT126ADTR2G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NLVVHCT126ADTR2G part is unused and in its original packaging.
Return procedure for NLVVHCT126ADTR2G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NLVVHCT126ADTR2G Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments
-
SN74LVC2G17DBVR
Texas Instruments
-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments
-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
