Texas Instruments NN325TRHARQ1
- Part No.:
- NN325TRHARQ1
- Manufacturer:
- Texas Instruments
- Category:
- Touch Screen Controllers
- Package:
- 40-VFQFN Exposed Pad
- Datasheet:
-
NN325TRHARQ1.pdf
- Description:
- IC SCREEN CNTRL 10BIT 40FN
- Quantity:
- Payment:

- Shipping:

Inventory:2,199
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Product details
Overview
NN325TRHARQ1 from Texas Instruments is an AEC-Q100 qualified automotive-grade ultra-low-power 16-bit RISC microcontroller optimized for multisensing touch applications. It integrates 32KB Flash, 1KB RAM, a 10-bit 200-ksps ADC with internal reference and DTC, dual 16-bit timers (Timer_A3 and Timer_B3), USCI_A0/USCI_B0 supporting UART/LIN/IrDA/SPI/I²C, and operates from 1.8 V to 3.6 V. It enables optical touch screen controllers requiring fast wake-up (<1 µs), brownout detection, and secure onboard programming.
For engineers reviewing the NN325TRHARQ1 datasheet, NN325TRHARQ1 pinout, NN325TRHARQ1 application, or NN325TRHARQ1 equivalent, this page delivers verified technical context, validated pin functions, real-world automotive touch use cases, and confirmed alternative options - all grounded in TI's SLAS824 December 2013 production data sheet.
Technical Context
The NN325TRHARQ1 implements the MSP430™ 16-bit RISC core with seven addressing modes, constant generators, and register-to-register execution in one CPU clock cycle. Its basic clock system supports four factory-calibrated DCO frequencies (1/8/12/16 MHz ±1%), 32-kHz crystal, HF crystal up to 16 MHz, resonator, or external resistor-based tuning.
It features five software-selectable low-power modes (LPM0–LPM4), with standby current as low as 0.7 µA and off-mode RAM retention at 0.1 µA. The integrated ADC10 includes autoscan, sample-and-hold, and data transfer controller (DTC) for autonomous conversion sequencing across 12 analog inputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | MSP430™ 16-bit RISC CPU with 16 general-purpose registers and 62.5-ns instruction cycle time at 16 MHz |
| Memory | 32KB Flash + 256B information memory + 1KB RAM; supports in-system programming via JTAG or BSL UART |
| ADC | 10-bit SAR ADC with 200-ksps sampling rate, internal reference, 12-channel autoscan, and DTC for zero-CPU-conversion chaining |
| Timers | Timer_A3 and Timer_B3, each with three capture/compare registers, supporting PWM, interval timing, and input capture |
| Communication | USCI_A0 (UART/LIN/IrDA/SPI) and USCI_B0 (SPI/I²C); LIN mode includes auto-baudrate detection per ISO 9141-2 |
| Power Management | Operating voltage 1.8–3.6 V; active mode 270 µA @ 1 MHz/2.2 V; standby mode 0.7 µA; off mode w/RAM retention 0.1 µA |
| Package | 40-pin QFN (RHA), 6 mm × 6 mm, 0.5 mm pitch, exposed thermal pad connected to DVSS |
Pinout & Package
The NN325TRHARQ1 is housed in a 40-pin QFN package (RHA) with 6 mm × 6 mm footprint, 0.5 mm lead pitch, and an exposed thermal pad recommended to be connected to DVSS for optimal thermal performance and noise immunity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P1.0/TACLK/ADC10CLK | Timer_A clock input / ADC conversion clock | Enables synchronous timer triggering and precise ADC sampling control; supports external clock injection or internal DCO routing |
| P2.3/TA1/A3/VREF−/VeREF− | Analog input / ADC reference negative | Provides dedicated low-impedance path for ADC reference ground or differential analog sensing on channel A3 |
| P3.4/UCA0TXD/UCA0SIMO | USCI_A0 transmit / SPI master-out | Configurable dual-function pin for UART TX or SPI MOSI; supports LIN-compliant enhanced UART with auto-baudrate detection |
| P4.6/TBOUTH/A15 | Timer_B output high-impedance / ADC channel A15 | Allows safe PWM output shutdown during fault conditions while retaining analog measurement capability on A15 |
| RST/NMI/SBWTDIO | Reset / non-maskable interrupt / Spy-Bi-Wire I/O | Single-pin debug interface for programming and test; supports fuse-protected security and brownout-triggered reset assertion |
Key Features
| Feature | Design Value |
|---|---|
| Brownout detector | Integrated circuitry asserts reset when supply drops below threshold; ensures deterministic startup and prevents erratic operation during voltage sag |
| Ultra-fast wake-up | DCO stabilizes in <1 µs from LPM4, enabling responsive touch event handling without latency penalties in battery-sensitive systems |
| Secure BSL | Bootstrap loader accessible via UART with user-defined password; protects firmware IP and enables field updates without JTAG hardware |
| Dual USCI modules | USCI_A0 and USCI_B0 operate independently-enabling simultaneous LIN bus communication and I²C sensor interfacing without resource contention |
| 16 I/O ports with configurable pullups/pulldowns | All 32 GPIO pins support individual direction, input/output, interrupt edge, and weak resistor control-critical for robust capacitive touch electrode routing |
Applications
| Automotive Touch Display Controller | Capacitive Touch Panel Interface |
|---|---|
Use Scenario: Integrated touch manager in center-stack infotainment displays requiring AEC-Q100 compliance and ESD-hardened signal acquisition. IC Role / Device Role / Timing Role: Primary MCU executing touch algorithm, managing ADC sampling across 12+ electrodes, and communicating results via LIN to host processor. Use Value: Sub-1 µs wake-up and 0.7 µA standby enable always-on touch responsiveness while meeting automotive battery drain budgets. |
Use Scenario: Dedicated front-end for projected-capacitive touch panels in instrument clusters with glove-mode and wet-finger operation. IC Role / Device Role / Timing Role: Multisensing engine performing synchronized charge-transfer measurements, noise filtering, and baseline tracking using ADC10 DTC and Timer_A3 PWM generation. Use Value: On-chip 10-bit ADC with internal reference and autoscan eliminates external precision references and reduces BOM count by two components. |
| Body Control Module Sensor Hub | Automotive LIN Node Controller |
Use Scenario: Consolidated sensor interface in door modules acquiring temperature, humidity, and proximity data alongside touch events. IC Role / Device Role / Timing Role: System controller aggregating analog sensor inputs (via ADC10 channels A0–A7), digital I/O status, and touch interrupts into unified CAN/LIN messages. Use Value: 32 GPIO with individually programmable pullups/pulldowns simplify direct connection to diverse sensors without external level-shifting or biasing networks. |
Use Scenario: Standalone LIN slave node managing backlight dimming, button feedback, and haptic response in steering-wheel controls. IC Role / Device Role / Timing Role: LIN protocol handler using USCI_A0 with auto-baudrate detection to adapt dynamically to master baud rates from 1.2 to 20 kbps per ISO 9141-2. Use Value: Eliminates need for external LIN transceiver in cost-sensitive nodes where physical layer is handled externally or via discrete drivers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-power automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MSP430F2617TRHAT | Same 40-pin RHA package; 116KB Flash, 8KB RAM, no automotive qualification; lacks brownout detector and LIN-specific UART features | Suitable for industrial prototypes but not certified for under-hood or dashboard deployment | Select only if AEC-Q100 compliance is unnecessary and higher memory is required for complex algorithms |
| TLV320AIC3106IRHBR | Audio codec IC-not a microcontroller; no Flash/RAM, no timers, no GPIO; focuses on analog audio path with integrated DAC/ADC | Designed for voice interface subsystems, not touch sensing or system control | Not functionally comparable; consider only if application shifts from touch management to audio processing |
Compared with MSP430F2617TRHAT, NN325TRHARQ1 trades memory capacity for automotive qualification, lower power, and touch-optimized peripherals; compared with TLV320AIC3106IRHBR, it provides full programmable control capability rather than fixed-function signal processing.
Availability
NN325TRHARQ1 is available at Aetrix Electronics and suitable for automotive infotainment systems, body electronics modules, and touch-enabled driver interfaces requiring stable component supply, long-term lifecycle assurance, and AEC-Q100-compliant sourcing.
Supply support for NN325TRHARQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies with over 50 years of automotive-grade product development experience.
NN325TRHARQ1 belongs to the MSP430x2xx ultra-low-power MCU family, designed specifically for battery-sensitive and safety-critical automotive human-machine interface (HMI) applications including touch sensing, sensor fusion, and LIN node control.
FAQ
What is the qualified temperature range for NN325TRHARQ1?
NN325TRHARQ1 is AEC-Q100 Grade 2 qualified, operating reliably from –40°C to +105°C ambient temperature. This rating covers typical automotive cabin and partial under-hood environments. The device undergoes stress testing per AEC-Q100 Rev-H requirements, including temperature cycling, HTOL, and ESD robustness validation. All parametric specifications in the SLAS824 datasheet apply within this range. NN325TRHARQ1 maintains 0.1 µA off-mode current and <1 µs wake-up across the full qualified range.
Does NN325TRHARQ1 support secure firmware updates in the field?
Yes, NN325TRHARQ1 supports secure field firmware updates via its password-protected bootstrap loader (BSL), accessible through USCI_A0 UART. The BSL implements flash write protection, password verification, and optional erase-lock mechanisms. Users define a custom 32-byte password stored in information memory; incorrect attempts trigger lockout. NN325TRHARQ1 does not require JTAG hardware for updates, enabling cost-effective OTA-like deployment in automotive gateways or telematics units.
How many analog input channels does the ADC10 support on NN325TRHARQ1?
The ADC10 module in NN325TRHARQ1 supports 12 dedicated analog input channels (A0–A7 and A12–A15), plus two reference voltage inputs (VREF+/VREF−). Channel mapping is fixed per pin assignment in the RHA package: P2.0–P2.4, P3.6–P3.7, and P4.3–P4.6 serve as analog inputs. All 12 channels are accessible simultaneously in autoscan mode with DTC-driven result storage, enabling rapid multi-electrode touch acquisition without CPU intervention. NN325TRHARQ1's ADC10 achieves 200-ksps throughput with internal 1.5-V reference.
Can NN325TRHARQ1 operate without an external crystal?
Yes, NN325TRHARQ1 can operate fully without an external crystal. Its digitally controlled oscillator (DCO) provides four factory-calibrated frequencies (1/8/12/16 MHz ±1%) usable immediately after reset. The internal very-low-power low-frequency oscillator (VLO) supplies ACLK at ~12 kHz for watchdog and RTC functions. External crystals (32 kHz or up to 16 MHz) are optional enhancements for higher timing accuracy or specific protocol requirements (e.g., LIN baud rate stability). NN325TRHARQ1 retains <1 µs wake-up and ultra-low-power operation using DCO alone.
What debug interface does NN325TRHARQ1 use?
NN325TRHARQ1 uses the two-wire Spy-Bi-Wire (SBW) interface via pins TEST/SBWTCK (RHA pin 37) and RST/NMI/SBWTDIO (RHA pin 5). SBW is TI's proprietary low-pin-count debug protocol compatible with MSP-FET and IAR/Code Composer Studio. It supports full JTAG functionality-including flash programming, real-time register inspection, and breakpoint debugging-using only two pins. Unlike standard JTAG, SBW requires no TMS or TDO pins, simplifying PCB layout. NN325TRHARQ1's SBW interface remains active even in LPM4, enabling deep-sleep debugging.
NN325TRHARQ1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 40-VFQFN Exposed Pad
- Touchscreen:
- -
- Resolution (Bits):
- 10 b
- Interface:
- I2C, SPI
- Voltage Reference:
- External, Internal
- Voltage - Supply:
- 1.8V ~ 3.6V
- Current - Supply:
- 390 µA
- Operating Temperature:
- -40°C ~ 105°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 40-VQFN (6x6)
NN325TRHARQ1 FAQ
1.How can I place an order for NN325TRHARQ1 through Aetrix?
Please submit a Request for Quotation (RFQ) for NN325TRHARQ1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NN325TRHARQ1 reliable?
The price and inventory of NN325TRHARQ1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NN325TRHARQ1 is usually 5 days.
3.What payment methods are accepted for NN325TRHARQ1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NN325TRHARQ1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NN325TRHARQ1?
NN325TRHARQ1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NN325TRHARQ1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NN325TRHARQ1?
For technical support, including NN325TRHARQ1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NN325TRHARQ1 requirements.
6.How does Aetrix verify that NN325TRHARQ1 is sourced from the original manufacturer or authorized distributors?
All NN325TRHARQ1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NN325TRHARQ1 meets industry standards.
7.What is the process for return or replacement of NN325TRHARQ1?
All NN325TRHARQ1 units undergo pre-shipment inspection (PSI). If there is an issue with NN325TRHARQ1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NN325TRHARQ1 part is unused and in its original packaging.
Return procedure for NN325TRHARQ1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NN325TRHARQ1 Tags
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