onsemi NOIX1SE9400B-LTI
- Part No.:
- NOIX1SE9400B-LTI
- Manufacturer:
- onsemi
- Category:
- Image Sensors, Camera
- Package:
- 163-BCLGA
- Datasheet:
-
NOIX1SE9400B-LTI.pdf
- Description:
- XGS9.4MP, 24PORT, COLOR 0
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
NOIX1SE9400B-LTI from onsemi is a 9.4 Megapixel global shutter CMOS image sensor with 3072 × 3072 active pixels, 3.2 µm pixel pitch, monochrome Bayer color filter array, and 24-lane HiSPi interface delivering 90 fps at 12-bit output - designed for high-speed machine vision inspection systems requiring motion artifact-free capture.
For engineers reviewing the NOIX1SE9400B-LTI datasheet, pinout, applications, or equivalent options, this page delivers verified technical context, validated pin functions, confirmed optical and electrical specifications, and real-world integration guidance for industrial camera design.
Technical Context
The NOIX1SE9400B-LTI implements a column-parallel 12-bit ADC architecture with on-chip digital gain (1/32× to 2× per channel), programmable ROI control for up to 8 regions, and context-switching across three register configurations. It uses a pipelined global shutter operation where integration of the next frame begins during readout of the current frame.
Timing is generated by an internal PLL locked to a 32.4 MHz EXTCLK input; HiSPi lane count is configurable (24/18/12/6 lanes), with each active lane operating at 777.6 Mbps. The sensor supports triggered integration and readout control via TRIG_INT and TRIG_RD inputs, and provides monitor outputs (MONITOR_0–2) for sequencer state visibility.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 3072 (H) × 3072 (V) active pixels - full-frame imaging area for 1/1.2-inch optical format (13.9 mm diagonal) |
| Pixel Size | 3.2 µm - enables high spatial resolution while maintaining quantum efficiency in visible/NIR spectrum |
| Shutter Type | Global shutter - eliminates motion blur for fast-moving objects in automated optical inspection |
| Output Interface | 24-lane HiSPi (Scalable Low-Voltage Signaling) - supports 90 fps at 12-bit depth with deterministic low-latency streaming |
| Frame Rate | 90 fps at 12-bit, 24-lane mode - meets real-time throughput requirements for high-speed production line cameras |
| Read Noise | < 4 e⁻ (1× analog gain), 1.9 e⁻ (4× analog gain) - ensures high signal fidelity in low-light industrial imaging |
| Dynamic Range | 68 dB - supports wide scene luminance variation without saturation or shadow clipping |
| Operating Temp. | −40°C to +85°C junction - qualified for uncontrolled factory-floor and outdoor ITS deployments |
Pinout & Package
NOIX1SE9400B-LTI is housed in a 163-pin Ceramic Land Grid Array (CLGA) package measuring 21 mm × 20 mm, optimized for thermal dissipation and mechanical stability in compact camera modules.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| DATA_[0:23]_P/N | HiSPi differential data lanes | 24 bidirectional LVDS pairs carrying serialized pixel data - requires 100 Ω termination at receiver end |
| D_CLK_[0:5]_P/N | HiSPi differential clock lanes | 6 clock pairs (max 2 active simultaneously) - D_CLK_2/D_CLK_3 used for top/bottom half readout synchronization |
| EXTCLK | External timing reference input | 32.4 MHz single-ended clock - serves as master reference for internal PLL and system timing derivation |
| RESET_N | Asynchronous hard reset | Active-low signal requiring ≥30 EXTCLK cycles low - initiates full hardware initialization sequence |
| TRIG_INT / TRIG_RD | Trigger control inputs | Edge-sensitive inputs enabling external synchronization of integration start and frame readout timing |
| MONITOR_0–2 | Sequencer state outputs | Three open-drain outputs indicating internal pipeline stage (e.g., integration active, readout active, idle) |
| FWSI_EN | Serial interface mode select | High = SPI (four-wire), Low = I²C (two-wire) - determines control interface protocol and pin usage (CS_N, SDATAOUT) |
| VDD_SLVS | HiSPi interface supply | 1.2 V (or 0.4 V) supply dedicated to HiSPi transceivers - decoupled separately to minimize jitter |
Key Features
| Feature | Design Value |
|---|---|
| On-chip 12-bit column ADCs | Enables parallel analog-to-digital conversion per column - eliminates rolling shutter artifacts and supports >90 fps full-resolution capture |
| Configurable HiSPi lane count | Supports 24/18/12/6 active lanes - allows bandwidth scaling for FPGA resource optimization or cost-driven interface simplification |
| Programmable ROI and context switching | Up to 8 independent regions of interest and 3 register contexts - enables multi-exposure HDR or rapid parameter switching between inspection tasks |
| Triggered integration and readout | Dual trigger inputs (TRIG_INT, TRIG_RD) - permits precise synchronization with conveyor motion, laser strobes, or external sensors |
| Monitor output pins | MONITOR_0–2 provide real-time visibility into sequencer state - accelerates debug of timing-critical camera firmware |
| Column-level analog gain | 1×, 2×, or 4× globally applied analog amplification - preserves SNR while adapting to varying illumination without increasing digital noise |
Applications
| Automated Optical Inspection (AOI) | Intelligent Transportation Systems (ITS) |
|---|---|
Use Scenario: High-speed PCB solder-joint verification on moving conveyors at >1 m/s. IC Role / Device Role / Timing Role: Global shutter image sensor capturing distortion-free frames synchronized to encoder pulses via TRIG_INT. Use Value: 90 fps full-resolution output enables sub-millisecond exposure control and eliminates motion blur - critical for detecting micro-cracks and bridging defects. | Use Scenario: License plate recognition at highway toll booths under variable lighting and vehicle speeds up to 160 km/h. IC Role / Device Role / Timing Role: Primary imaging sensor with programmable ROI targeting license plate region and dynamic exposure adjustment via digital gain. Use Value: 68 dB dynamic range and <4 e⁻ read noise ensure legible character capture in mixed daylight/headlight conditions without overexposure or noise degradation. |
| Medical Endoscopy Imaging | Broadcast Studio Camera |
Use Scenario: Miniaturized rigid endoscope requiring high-resolution, low-noise imaging in confined anatomical spaces. IC Role / Device Role / Timing Role: Image capture element interfaced to FPGA-based video processor via 24-lane HiSPi for minimal latency and maximum bandwidth. Use Value: 3.2 µm pixel size balances resolution and sensitivity in constrained illumination - enabling diagnostic clarity without excessive LED heating. | Use Scenario: 4K/UHD studio camera head requiring artifact-free imaging of fast-moving talent and graphics overlays. IC Role / Device Role / Timing Role: Core sensor providing global shutter capture synchronized to genlock signals via external trigger inputs. Use Value: Pipelined integration/readout and context switching allow seamless transition between exposure modes during live broadcast - no frame drop or corruption. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar global shutter CMOS image sensor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NOIX2SE9400B-LTI | 12-lane HiSPi interface (vs. 24-lane); lower max frame rate (56 fps at 12-bit) | Targeted at cost-sensitive or FPGA I/O-constrained designs where full 90 fps is not required | Select when system bandwidth or FPGA pin count limits justify trade-off in speed for reduced complexity |
| NOIX1SE8000B-LTI | 8.8 Mp resolution (4096 × 2160), 1/1.1-inch optical format, higher max frame rate (128 fps at 24-lane) | Better suited for wide-field-of-view applications needing faster frame rates over slightly lower vertical resolution | Choose for applications prioritizing temporal resolution over pixel count - e.g., high-speed motion analysis with moderate spatial detail |
Compared with NOIX1SE9400B-LTI, NOIX2SE9400B-LTI reduces interface complexity and power at the cost of frame rate, while NOIX1SE8000B-LTI trades vertical resolution for higher temporal sampling - both serve distinct system-level trade-offs in bandwidth, resolution, and speed.
Availability
NOIX1SE9400B-LTI is available at Aetrix Electronics and suitable for machine vision, intelligent transportation systems, and medical imaging applications requiring stable component supply, long-term manufacturability, and RoHS-compliant sourcing.
Supply support for NOIX1SE9400B-LTI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi is a global semiconductor supplier focused on energy-efficient innovation, delivering silicon solutions for automotive, industrial, cloud, and medical markets with emphasis on reliability and performance.
The XGS family - including NOIX1SE9400B-LTI - was engineered specifically for high-speed, high-resolution industrial imaging, combining global shutter accuracy with scalable HiSPi bandwidth to replace legacy CCD and rolling-shutter CMOS architectures.
FAQ
What is the optical format and active pixel resolution of the NOIX1SE9400B-LTI?
The NOIX1SE9400B-LTI features a 1/1.2-inch optical format (13.9 mm diagonal) and 3072 × 3072 active pixels, totaling 9.4 megapixels. Its 3.2 µm pixel pitch and global shutter architecture enable high-fidelity capture of fast-moving objects without motion distortion - a key requirement for precision AOI and ITS deployments where NOIX1SE9400B-LTI is commonly deployed.
Does the NOIX1SE9400B-LTI support both I²C and SPI serial interfaces?
Yes, the NOIX1SE9400B-LTI supports dual serial interfaces: Two-Wire I²C and Four-Wire SPI. Interface selection is controlled by the FWSI_EN pin - high for SPI (requiring CS_N and SDATAOUT), low for I²C (with SCLK/SDATA pulled up to VDD_IO). This flexibility allows designers to choose based on configuration speed needs or existing controller capabilities in their NOIX1SE9400B-LTI-based camera system.
What is the maximum frame rate and bit depth supported by the NOIX1SE9400B-LTI?
The NOIX1SE9400B-LTI achieves 90 fps at 12-bit depth using all 24 HiSPi lanes. In 10-bit mode, it supports up to 100 fps at full resolution. Frame rate scales inversely with active lane count: 56 fps at 12-bit with 12 lanes (NOIX2SE9400B-LTI variant), and 28 fps with 6 lanes. These values are measured under standard conditions with 32.4 MHz EXTCLK and confirmed in the official NOIX1SE9400B-LTI datasheet.
How does the NOIX1SE9400B-LTI handle power sequencing during startup?
The NOIX1SE9400B-LTI requires strict power-up sequencing: VDD_IO first, followed by VDD_PLL, VDD, VAA, then VAA_PIX/VAA_PIX_BST/VAA_RD, and finally VDD_SLVS. EXTCLK must be stable before asserting RESET_N for ≥30 cycles. This sequence ensures proper PLL lock, analog block initialization, and HiSPi interface readiness - deviations risk unstable operation or failure to reach STANDBY state, as documented for NOIX1SE9400B-LTI.
Can the NOIX1SE9400B-LTI be used with different color filter arrays?
The NOIX1SE9400B-LTI is specified with a Bayer color filter array (CFA) for RGB imaging. Monochrome variants (e.g., NOIX1SN9400B-LTI) exist in the same XGS 9400 family but use no CFA - offering higher quantum efficiency and no demosaicing artifacts. The NOIX1SE9400B-LTI's CFA is fixed and integrated during fabrication; no field-selectable or removable filter option exists for this specific part number.
NOIX1SE9400B-LTI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- -
- Package/Case:
- 163-BCLGA
- Packaging:
- Tray
- Product Status:
- Active
- Type:
- CMOS
- Pixel Size:
- 3.2µm x 3.2µm
- Active Pixel Array:
- 3072H x 3072V
- Frames per Second:
- 90.0
- Voltage - Supply:
- 1.7V ~ 1.9V, 2.7V ~ 2.9V
- Supplier Device Package:
- 163-CLGA (20.88x19.9)
- Operating Temperature:
- -40°C ~ 85°C (TJ)
- Grade:
- -
- Qualification:
- -
NOIX1SE9400B-LTI FAQ
1.How can I place an order for NOIX1SE9400B-LTI through Aetrix?
Please submit a Request for Quotation (RFQ) for NOIX1SE9400B-LTI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NOIX1SE9400B-LTI reliable?
The price and inventory of NOIX1SE9400B-LTI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NOIX1SE9400B-LTI is usually 5 days.
3.What payment methods are accepted for NOIX1SE9400B-LTI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NOIX1SE9400B-LTI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NOIX1SE9400B-LTI?
NOIX1SE9400B-LTI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NOIX1SE9400B-LTI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NOIX1SE9400B-LTI?
For technical support, including NOIX1SE9400B-LTI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NOIX1SE9400B-LTI requirements.
6.How does Aetrix verify that NOIX1SE9400B-LTI is sourced from the original manufacturer or authorized distributors?
All NOIX1SE9400B-LTI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NOIX1SE9400B-LTI meets industry standards.
7.What is the process for return or replacement of NOIX1SE9400B-LTI?
All NOIX1SE9400B-LTI units undergo pre-shipment inspection (PSI). If there is an issue with NOIX1SE9400B-LTI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NOIX1SE9400B-LTI part is unused and in its original packaging.
Return procedure for NOIX1SE9400B-LTI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NOIX1SE9400B-LTI Tags

-
MT9M114EBLSTCZ-CR
onsemi

-
EPC611-CSP24-001
ESPROS Photonics AG

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AR0147ATSC00XUEG5-DRBR
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AR0130CSSM00SPCA0-DRBR
onsemi

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AR1335CSSC11SMKA0-CP
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AR0521SR2M09SURA0-DP
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AR0135CS2M25SUEA0-DPBR
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AR0522SRSC09SURA0-DP
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AR0134CSSC00SPCA0-DPBR
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AR0134CSSM00SUEA0-DPBR
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AR0521SR2C09SURA0-DP
onsemi
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AR0135CS2M00SUEA0-DPBR
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