NXP Semiconductors NX5DV713EHF,118
- Part No.:
- NX5DV713EHF,118
- Manufacturer:
- NXP Semiconductors
- Category:
- Video Processing
- Package:
- 32-WFQFN Exposed Pad
- Datasheet:
-
NX5DV713EHF,118.pdf
- Description:
- IC VIDEO VGA 32HWQFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,006
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Product details
Overview
NX5DV713EHF,118 from NXP Semiconductors is a dual-supply 1-to-2 VGA switch IC designed for routing RGB, H-sync, V-sync, and DDC signals between a graphics controller and two independent VGA ports. It features 4 Ω typical ON resistance, 12 pF typical ON capacitance, 50 ps output skew, <2 μA quiescent current, and operates across −40 °C to +85 °C. It enables seamless dual-display switching in space-constrained notebook docking stations.
For engineers reviewing the NX5DV713EHF,118 datasheet, NX5DV713EHF,118 pinout, NX5DV713EHF,118 application, or NX5DV713EHF,118 equivalent, this page delivers verified electrical parameters, thermal-enhanced HWQFN32 package details, level-translating sync/DDC functionality, and real-world implementation guidance for VGA signal routing in embedded display systems.
Technical Context
The NX5DV713EHF,118 integrates three identical high-bandwidth SPDT RGB switches with matched ON resistance (4 Ω typ) and low flatness (0.5 Ω), plus dual-level-translating buffers for H/V-sync (VCC(A)-referenced inputs, VCC(B)-referenced outputs) and two SPDT DDC switches with diode-drop clamping. Its break-before-make timing (10 ns) prevents signal contention during channel switching.
It supports asymmetric dual-rail operation: VCC(A) = 2.0–5.5 V (e.g., 3.3 V for DDC clamping), VCC(B) = 4.5–5.5 V (e.g., 5.0 V for TTL-compliant sync outputs), enabling compatibility with low-voltage graphics controllers driving standard 5 V VGA loads while maintaining I²C DDC compliance.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ON Resistance | 4 Ω typical - ensures minimal RGB signal attenuation and preserves video integrity up to 600 MHz bandwidth |
| ON Capacitance | 12 pF typical - maintains high-frequency VGA signal fidelity with low capacitive loading on source |
| Output Skew | 50 ps maximum - guarantees tight timing alignment across R/G/B channels for color accuracy |
| Propagation Delay | 3 ns typical (H0→H1/H2, V0→V1/V2) - enables fast, glitch-free sync switching without display artifacts |
| Supply Current | <2 μA total - allows integration into always-on display management circuits without impacting system power budget |
| −3 dB Bandwidth | 600 MHz - supports full-resolution analog VGA (up to 1920×1200 @ 60 Hz) without high-frequency roll-off |
| Crosstalk | −50 dB at 50 MHz - isolates active and inactive VGA channels to prevent ghosting or interference |
Pinout & Package
HWQFN32 plastic thermal-enhanced very very thin quad flat package (SOT1180-1); 32-terminal, no-lead construction; body dimensions 3.0 × 6.0 × 0.75 mm; exposed thermal pad (non-electrical, floating or GND-connected).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| R0, G0, B0 (Pins 1, 2, 5) | RGB input/output common node | Accepts analog RGB signals from graphics controller; routed to either port 1 or port 2 based on SEL state |
| R1, G1, B1 (Pins 27, 25, 22) | Port 1 RGB output | Delivers switched RGB to first VGA monitor; referenced to VCC(B) for 5 V TTL-level drive |
| R2, G2, B2 (Pins 26, 24, 21) | Port 2 RGB output | Delivers switched RGB to second VGA monitor; electrically isolated from Port 1 when inactive |
| H0, V0 (Pins 6, 7) | H-sync/V-sync input | VCC(A)-referenced inputs accepting 2.0–5.5 V logic; level-translated to VCC(B) outputs |
| H1, V1 (Pins 20, 18) | Port 1 sync output | VCC(B)-referenced TTL-compatible outputs (VOH ≥ VCC(B)−0.5 V, VOL ≤ 0.5 V) for VGA port 1 |
| H2, V2 (Pins 19, 17) | Port 2 sync output | Identical TTL drive capability as H1/V1; disabled (high-Z) when SEL selects Port 1 |
| SDA0, SCL0 (Pins 9, 10) | DDC input | I²C bidirectional data/clock inputs referenced to VCC(A); clamped to VCC(A)−0.7 V max for VESA compliance |
| SDA1, SCL1 (Pins 12, 14) | Port 1 DDC output | Active SPDT path to first VGA monitor's EDID EEPROM; supports standard 100 kHz I²C |
| SDA2, SCL2 (Pins 13, 15) | Port 2 DDC output | Active SPDT path to second VGA monitor's EDID; automatically isolated when not selected |
| SEL (Pin 30) | Channel select input | Active-HIGH control: logic HIGH routes all signals to Port 2 (R2/G2/B2/H2/V2/SDA2/SCL2) |
| VCC(A) (Pins 4, 23, 32) | Input-side supply | Powers RGB switches, sync input buffers, and DDC clamping circuitry; sets DDC voltage reference |
| VCC(B) (Pin 16) | Output-side supply | Powers sync output buffers and DDC output drivers; defines TTL output swing for H/V outputs |
| GND (Pins 3, 11, 28, 31) | Ground reference | Four dedicated ground terminals minimize ground bounce and ensure stable switching performance |
Key Features
| Feature | Design Value |
|---|---|
| Dual-rail level translation | VCC(A) = 2.0–5.5 V / VCC(B) = 4.5–5.5 V enables low-voltage GPU interfacing with standard 5 V VGA loads |
| Over-voltage tolerant inputs | Withstands −0.5 V to +6 V on all pins - protects against hot-plug transients and ESD-induced overvoltage |
| Integrated DDC multiplexing | Two SPDT I²C switches with diode-drop clamping eliminate need for external level shifters in EDID communication paths |
| Break-before-make switching | 10 ns guaranteed tb-m prevents short-circuit between VGA ports during channel transition |
| ESD robustness | HBM >4 kV, CDM >1000 V, IEC61000-4-2 contact >4 kV - meets industrial-grade reliability requirements |
Applications
| Notebook Docking Stations | Digital Projectors |
|---|---|
Use Scenario: A single laptop connects to two external VGA displays via a compact docking station. IC Role / Device Role / Timing Role: NX5DV713EHF,118 routes RGB, sync, and DDC signals from the laptop GPU to either of two VGA outputs under software control. Use Value: Enables seamless dual-monitor selection without manual cable swapping; preserves EDID handshaking for automatic resolution detection on both ports. |
Use Scenario: A digital projector with dual VGA inputs accepts content from either a PC or media player. IC Role / Device Role / Timing Role: NX5DV713EHF,118 acts as a front-end signal selector, presenting clean, level-shifted VGA signals to the projector's video processing ASIC. Use Value: Eliminates signal degradation from passive splitters; maintains 600 MHz bandwidth for full HD video without color fringing or sync jitter. |
| Computer Monitors | Servers with KVM |
Use Scenario: A multi-input monitor supports simultaneous connection to desktop and laptop, with user-selectable source. IC Role / Device Role / Timing Role: NX5DV713EHF,118 serves as the core VGA multiplexer, switching all analog video and control signals in unison under microcontroller command. Use Value: Ensures pixel-perfect RGB alignment and zero-latency sync switching - critical for professional graphics applications requiring flicker-free transitions. |
Use Scenario: A server rack-mounted KVM switch routes VGA output from multiple servers to a single console monitor. IC Role / Device Role / Timing Role: NX5DV713EHF,118 provides per-server VGA signal isolation and level translation in the KVM's signal path. Use Value: Prevents cross-talk between server video streams; supports hot-swap detection via reliable DDC handshaking on each channel. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar VGA signal switching applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TS3V330RGTR | Single-supply (3.3 V only); no level translation; lower −3 dB bandwidth (350 MHz) | Restricted to 3.3 V systems; unsuitable for mixed-voltage VGA routing with 5 V sync outputs | Select only if both source and display operate at 3.3 V and bandwidth ≤350 MHz suffices |
| PI3CH401LEX | Single-pole single-throw (SPST) architecture; requires external buffers for sync/DDC; no integrated DDC clamping | Needs additional components for full VGA functionality; increases PCB area and BOM count | Choose when discrete control of RGB vs. sync paths is required, and board space permits added support circuitry |
Compared with TS3V330RGTR and PI3CH401LEX, the NX5DV713EHF,118 uniquely integrates dual-rail level translation, DDC multiplexing with clamping, and matched RGB switching in one HWQFN32 package - reducing component count, layout complexity, and validation effort for dual-VGA endpoint designs.
Availability
NX5DV713EHF,118 is available at Aetrix Electronics and suitable for notebook docking stations, digital projectors, and computer monitors requiring stable component supply, industrial temperature operation (−40 °C to +85 °C), and high-fidelity analog video routing.
Supply support for NX5DV713EHF,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and consumer applications.
The NX5DV713EHF,118 belongs to NXP's high-speed analog switch portfolio, engineered specifically for robust, low-distortion VGA signal routing in space-constrained portable and embedded display systems.
FAQ
What is the recommended supply voltage configuration for NX5DV713EHF,118 in a typical dual-VGA setup?
For standard operation, configure VCC(A) = 3.3 V to enable DDC signal clamping for VESA I²C compliance, and VCC(B) = 5.0 V to provide TTL-compatible H/V-sync outputs. This dual-rail setup allows low-voltage graphics controllers to drive 5 V VGA monitors while preserving EDID communication integrity - a key requirement validated in the NX5DV713EHF,118 datasheet under Recommended Operating Conditions.
Does NX5DV713EHF,118 support hot-plug detection for connected VGA monitors?
Yes, NX5DV713EHF,118 supports hot-plug detection through its integrated DDC multiplexer: SDA0/SCL0 inputs monitor the I²C bus, and the selected port (SDA1/SCL1 or SDA2/SCL2) actively communicates with the monitor's EDID EEPROM. The device's over-voltage tolerant inputs (−0.5 V to +6 V) and 4 kV HBM ESD rating ensure robustness during live insertion - confirmed in the Electrical Characteristics and ESD Protection sections of the NX5DV713EHF,118 product data sheet.
Can NX5DV713EHF,118 be used with non-standard sync signal levels, such as 1.8 V graphics controllers?
Yes, NX5DV713EHF,118 accepts H0/V0 inputs down to 2.0 V minimum (VIH = 2 V at VCC(A) = 3 V), making it compatible with 2.5 V and 3.3 V controllers. For 1.8 V sources, external level-shifting is required before H0/V0, as the NX5DV713EHF,118's input thresholds are not specified below 2.0 V - a constraint explicitly documented in Table 8 (Static Characteristics) of the NX5DV713EHF,118 datasheet.
How does the break-before-make timing of NX5DV713EHF,118 prevent signal corruption during switching?
The NX5DV713EHF,118 guarantees a 10 ns minimum break-before-make interval (tb-m) between channel transitions, ensuring that the previously selected VGA port is fully disconnected before the new port is enabled. This eliminates momentary short-circuits between outputs, preventing sync glitches, RGB crosstalk, or EDID bus contention - behavior verified in Figure 12 and Table 9 (Dynamic Characteristics) of the NX5DV713EHF,118 datasheet.
Is the thermal pad on the HWQFN32 package of NX5DV713EHF,118 electrically connected?
No, the exposed thermal pad on the NX5DV713EHF,118's SOT1180-1 (HWQFN32) package is mechanically attached to the die substrate using conductive die attach material but has no electrical function. As stated in Section 6.2 Pin Description, it may remain floating or be connected to GND for thermal enhancement - soldering is optional and imposes no electrical requirement, per the official NX5DV713EHF,118 package documentation.
NX5DV713EHF,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 32-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Function:
- Switch
- Applications:
- Consumer Video
- Standards:
- -
- Control Interface:
- I2C
- Voltage - Supply:
- 2.0V ~ 5.5V, 4.5V ~ 5.5V
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 32-HWQFN (3x6)
NX5DV713EHF,118 FAQ
1.How can I place an order for NX5DV713EHF,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for NX5DV713EHF,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NX5DV713EHF,118 reliable?
The price and inventory of NX5DV713EHF,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NX5DV713EHF,118 is usually 5 days.
3.What payment methods are accepted for NX5DV713EHF,118?
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4.How is shipping managed for NX5DV713EHF,118?
NX5DV713EHF,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NX5DV713EHF,118 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NX5DV713EHF,118?
For technical support, including NX5DV713EHF,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NX5DV713EHF,118 requirements.
6.How does Aetrix verify that NX5DV713EHF,118 is sourced from the original manufacturer or authorized distributors?
All NX5DV713EHF,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NX5DV713EHF,118 meets industry standards.
7.What is the process for return or replacement of NX5DV713EHF,118?
All NX5DV713EHF,118 units undergo pre-shipment inspection (PSI). If there is an issue with NX5DV713EHF,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NX5DV713EHF,118 part is unused and in its original packaging.
Return procedure for NX5DV713EHF,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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