Nexperia USA Inc. NXU0204BQX

Overview

NXU0204BQX from Nexperia is a 4-bit dual-supply voltage level translating buffer with Schmitt-trigger inputs and 3-state outputs, designed for bidirectional asynchronous bus translation between independent 0.9 V–5.5 V domains. It supports fixed-direction data flow (A→B on three channels, B→A on one), features integrated 6.5 MΩ input pull-down resistors, IOFF partial power-down protection, and operates across –40 °C to +125 °C for industrial embedded I/O bridging.

For engineers reviewing the NXU0204BQX datasheet, NXU0204BQX pinout, NXU0204BQX application, or NXU0204BQX equivalent, key selection criteria include dual-rail supply flexibility (VCCA/VCCB = 0.9–5.5 V), Schmitt-trigger noise immunity, 250 Mbps max data rate at ≥1.8 V, 12 mA output drive at 5 V, and suspend-mode behavior during supply loss.

Technical Context

The NXU0204BQX implements independent A-side (VCCA) and B-side (VCCB) supply domains with four unidirectional data paths: A1/A2 → YB1/YB2 (A-to-B), B3/B4 → YA3/YA4 (B-to-A). Its Schmitt-trigger inputs provide hysteresis (e.g., 0.96 V typ at 5.5 V), enabling robust operation with slow or noisy signals, while internal static pull-downs prevent floating inputs.

Output enable (OE) is referenced to either VCCA or VCCB via VCC(MIN) circuitry; OE low forces all outputs into high-impedance state. The device enters suspend mode (Hi-Z) when either supply drops below 100 mV or floats, and IOFF blocks backflow current during partial power-down-eliminating need for supply sequencing and preventing glitches during power transitions.

Key Specifications

Pinout & Package

DHVQFN14 package (SOT762-1), 2.5 × 3 × 0.85 mm body, 14-terminal leadless thermal-enhanced quad flat; exposed thermal pad (GND(1)) recommended floating or connected to GND.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar voltage translation applications.

Compared with NXU0104BQX, NXU0204BQX delivers double channel density for bus-level translation; versus NXU0304BQX, it offers 2× lower propagation delay and deterministic signal routing-critical for timing-critical SPI and JTAG links.

Availability

NXU0204BQX is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, automotive body control modules, and consumer IoT hub interface designs requiring stable component supply across extended temperature ranges and mixed-voltage architectures.

Supply support for NXU0204BQX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, power, analog, and MOSFET solutions for automotive, industrial, and consumer markets.

The NXU series targets mixed-voltage system integration, with the NXU0204 specifically engineered for robust, low-glitch bidirectional level translation in harsh electromagnetic environments and thermally demanding applications.

FAQ

Can NXU0204BQX translate between 0.9 V and 5.5 V simultaneously?

Yes. VCCA and VCCB may be independently set from 0.9 V to 5.5 V, enabling direct translation between any pair of logic domains in that range-including 0.9 V ↔ 5.5 V. Input thresholds scale with supply voltage, and output drive remains functional across the full range, verified per JEDEC standards JESD8-12 through JESD12-6.

What happens if OE is left floating during power-up?

The OE pin has no internal pull-up; if left floating, its state is undefined until VCCA or VCCB reaches ~0.5 V, risking brief output contention. Nexperia recommends pulling OE low externally (e.g., via 10 kΩ to GND) or connecting it to a controlled GPIO to ensure Hi-Z state during all power transitions, including cold start and brown-out recovery.

Does NXU0204BQX support true bidirectional data flow on all channels?

No. It provides fixed-direction translation: A1/A2 → YB1/YB2 (A-to-B) and B3/B4 → YA3/YA4 (B-to-A). This asymmetric architecture optimizes timing and drive strength per path. For fully bidirectional per-channel operation, consider the pin-compatible NXU0304BQX, which adds direction-control logic at the cost of higher propagation delay.

How does the IOFF circuit protect during partial power-down?

When either VCCA or VCCB falls below 100 mV or becomes floating, the IOFF circuit disables internal conduction paths, limiting output leakage to ≤2 μA. This prevents back-current from an active supply into a powered-down domain-protecting downstream ICs and avoiding latch-up in systems with mismatched power sequencing, such as modular compute blades.