Nexperia USA Inc. NXU0304PWJ
- Part No.:
- NXU0304PWJ
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Translators, Level Shifters
- Package:
- Datasheet:
-
NXU0304PWJ.pdf
- Description:
- NXU0304PW/SOT402/TSSOP14
- Quantity:
- Payment:

- Shipping:

Inventory:100
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Product details
Overview
NXU0304PWJ from Nexperia is a 4-bit dual-supply voltage level translating buffer with Schmitt-trigger inputs and 3-state outputs, designed for bidirectional asynchronous bus translation between 0.9 V–5.5 V domains. It supports fixed-direction data flow (A→B on three channels, B→A on one channel), features independent VCCA/VCCB supplies, integrated 6.5 MΩ input pull-downs, and IOFF circuitry enabling partial power-down operation in mixed-voltage systems such as industrial I/O controllers.
For engineers reviewing the NXU0304PWJ datasheet, NXU0304PWJ pinout, NXU0304PWJ application, or NXU0304PWJ equivalent, this device is selected for robust level translation in noisy environments, low-power embedded interfaces, and applications requiring glitch-free power sequencing across disparate supply rails (e.g., 1.8 V MCU to 3.3 V peripheral).
Technical Context
The NXU0304PWJ implements four independent translation paths with asymmetric directionality: A1–A3 drive YB1–YB3 (A→B), while B4 drives YA4 (B→A). Its Schmitt-trigger inputs provide 0.25–1.18 V hysteresis (depending on supply) to reject slow/noisy signals, and the OE pin operates referenced to either VCCA or VCCB via internal VCC(MIN) logic.
IOFF protection activates when either VCCA or VCCB drops below 100 mV or floats, forcing all outputs into high-impedance state and blocking backflow current. No power-supply sequencing is required, and output glitches are suppressed during power-up/down transitions due to synchronized suspend-mode entry.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply range (VCCA/VCCB) | 0.9 V to 5.5 V each - enables translation between any common logic nodes (1.2 V, 1.8 V, 2.5 V, 3.3 V, 5.0 V) without level-shifter ICs. |
| Max data rate | 250 Mbps (≥1.8 V → 5 V) - supports high-speed UART, SPI, and JTAG interfaces with timing margin. |
| Input hysteresis (VH) | 0.25 V to 1.18 V (typ.) - ensures noise immunity for slow-rising signals and eliminates metastability in noisy industrial environments. |
| IOFF leakage | <±2 µA at -40 °C to +125 °C - prevents damaging back-current when one rail is powered down, critical for hot-swap and battery-backed systems. |
| Output drive (IOH/IOL) | ±12 mA at 4.5 V - provides sufficient fan-out to drive multiple CMOS loads or moderate PCB trace capacitance without external buffers. |
| Static current (ICC) | 3 µA at 25 °C, 5 µA over full temp range - enables always-on translation in ultra-low-power IoT sensor nodes. |
| ESD rating | HBM ±2500 V, CDM ±1500 V - exceeds JEDEC Class 2/3 requirements for handling robustness in manufacturing and field deployment. |
Pinout & Package
TSSOP14 package (SOT402-1), 14-lead plastic thin shrink small outline, 4.4 mm body width, 0.65 mm pitch. Pin 1 index located at lower-left corner below marking code.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCCA | Supply for A-side inputs (A1–A3, YA4) | Reference for An inputs and YA4 output; sets input threshold and output HIGH level on A-side path. |
| VCCB | Supply for B-side inputs (B4) and outputs (YB1–YB3) | Reference for B4 input and YBn outputs; defines translation target voltage domain for three channels. |
| A1–A3 | Data inputs (A-side) | Unidirectional inputs driving YB1–YB3; Schmitt-triggered with 6.5 MΩ internal pull-down. |
| B4 | Data input (B-side) | Single input driving YA4; referenced to VCCB, enabling B→A translation on dedicated channel. |
| YB1–YB3 | Data outputs (B-side) | 3-state outputs driven by A1–A3; high-impedance when OE = LOW; referenced to VCCB. |
| YA4 | Data output (A-side) | 3-state output driven by B4; high-impedance when OE = LOW; referenced to VCCA. |
| OE | Output enable (active HIGH) | Referenced to VCCA or VCCB via VCC(MIN); floating or pulled LOW ensures Hi-Z at power-up/power-down. |
| GND | Ground reference | Common return for both supply domains; required for proper IOFF and ESD clamp operation. |
| n.c. | No-connect terminals | Pins 6 and 9 (TSSOP14) are unconnected - must be left floating or grounded per layout guidelines. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-supply translation | Independent VCCA/VCCB (0.9–5.5 V) enables flexible inter-domain signaling without external biasing or resistive dividers. |
| Schmitt-trigger inputs | Integrated 6.5 MΩ pull-down + programmable VT+/VT− thresholds ensure reliable latching of slow or noisy signals (e.g., mechanical switch inputs). |
| IOFF partial power-down | Automatic Hi-Z output disable and <±2 µA leakage when either supply falls below 100 mV or floats - eliminates need for external isolation switches. |
| Glitch-free power sequencing | No power-supply ramp order required; suspend mode activation prevents output transients during VCCA/VCCB transitions. |
| JEDEC-compliant voltage standards | Fully compliant with JESD8-12 through JESD12-6 - certified for use in 0.9 V to 5.5 V logic families across consumer, industrial, and automotive applications. |
Applications
| Industrial I/O Expansion | Low-Power Sensor Interface |
|---|---|
|
Use Scenario: Connecting 1.8 V microcontroller GPIOs to legacy 3.3 V industrial PLC modules with long cable runs in electrically noisy factory floors. IC Role / Device Role / Timing Role: Bidirectional voltage translator providing noise-immune signal integrity and IOFF isolation during controller sleep cycles. Use Value: Eliminates external RC filters and discrete MOSFET translators while maintaining 250 Mbps throughput and sub-1 ns output skew. |
Use Scenario: Interfacing ultra-low-power environmental sensors (1.2 V supply) to a 2.5 V data acquisition SoC in battery-powered edge nodes. IC Role / Device Role / Timing Role: Level-shifting buffer with 3 µA quiescent current and Schmitt-triggered inputs tolerating slow analog-to-digital wake-up signals. Use Value: Reduces system standby power by 40% vs. standard translators and prevents false triggers from EMI-induced input bounce. |
| Embedded Debug Port Isolation | Multi-Rail FPGA Configuration |
|
Use Scenario: Isolating JTAG/SWD debug lines between a 3.3 V host debugger and a 1.1 V FPGA core during firmware development and field updates. IC Role / Device Role / Timing Role: Direction-controlled level translator with OE-gated 3-state outputs enabling safe hot-plug debugging without bus contention. Use Value: Supports 100+ Mbps JTAG clock rates while preventing damage from supply mismatch during probe attachment/removal. |
Use Scenario: Translating configuration bitstream signals from a 1.8 V PROM to a 2.5 V FPGA configuration bank with strict setup/hold timing. IC Role / Device Role / Timing Role: Low-skew (≤0.7 ns) unidirectional translator ensuring deterministic timing margins for FPGA startup sequences. Use Value: Guarantees reliable configuration loading across temperature (-40 °C to +125 °C) with no rework needed for voltage node changes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-supply level translation applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NXU0104PW | 2-bit version, identical VCCA/VCCB range and Schmitt inputs but half the channel count and no B→A path. | Limited to simpler point-to-point links; lacks dedicated B→A channel for bidirectional control signals. | Select when only two A→B channels are needed and board space is constrained. |
| NXU0204PW | 4-bit with symmetric A↔B bidirectionality on all channels (no fixed-direction architecture); higher propagation delay (up to 45 ns). | Better suited for fully bidirectional buses (e.g., I²C), but less optimal for asymmetric protocols like SPI where direction is static. | Choose for protocols requiring dynamic direction reversal; avoid when minimizing propagation delay is critical. |
Compared with NXU0104PW and NXU0204PW, the NXU0304PWJ offers unique asymmetric channel allocation (3× A→B + 1× B→A), lowest propagation delay (26.5 ns min), and highest data rate (250 Mbps), making it optimal for mixed-direction embedded interfaces where timing and channel specialization matter.
Availability
NXU0304PWJ is available at Aetrix Electronics and suitable for industrial I/O expansion, low-power sensor interface, and embedded debug port isolation requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for NXU0304PWJ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a leading semiconductor manufacturer specializing in high-performance logic, analog, and discrete components, with global R&D and manufacturing facilities focused on reliability and energy efficiency.
The NXU0304 belongs to Nexperia's dual-supply level translation product line, engineered specifically for robust, low-power, mixed-voltage system interfacing in industrial automation, IoT edge devices, and embedded computing platforms.
FAQ
Can NXU0304PWJ translate between 0.9 V and 5.5 V simultaneously?
Yes. VCCA and VCCB can be independently set from 0.9 V to 5.5 V, enabling direct translation between these extremes - for example, a 0.9 V ASIC core communicating with a 5.5 V industrial actuator driver. The device guarantees specified timing and drive strength across the full range, validated per JEDEC standards JESD8-12 and JESD12-6.
What happens if OE is left unconnected during power-up?
The OE pin has no internal pull-up; however, its VCC(MIN) circuitry allows safe floating. When OE is floating or pulled LOW, all outputs enter high-impedance state - preventing bus contention during power sequencing. This behavior is explicitly characterized in the datasheet's suspend-mode section and requires no external components.
Does NXU0304PWJ support hot-swap between powered and unpowered domains?
Yes. The IOFF circuitry activates when either VCCA or VCCB drops below 100 mV or floats, disabling outputs and limiting backflow current to <±2 µA. This protects live circuits during hot-insertion of daughterboards or modular peripherals, satisfying IEC 61000-4-2 Level 4 ESD and partial-power-down requirements.
How does the Schmitt-trigger input improve noise immunity compared to standard CMOS inputs?
The NXU0304PWJ's Schmitt inputs provide 0.25–1.18 V hysteresis (depending on supply), meaning the rising and falling thresholds differ significantly - e.g., VT+ = 0.89 V and VT− = 0.50 V at 1.4 V supply. This prevents oscillation on slow-rising edges and rejects noise spikes narrower than the hysteresis window, unlike standard CMOS inputs with near-zero hysteresis.
NXU0304PWJ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- -
- Package/Case:
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Translator Type:
- Voltage Level
- Channel Type:
- Unidirectional
- Number of Circuits:
- 1
- Channels per Circuit:
- 4
- Voltage - VCCA:
- 0.9 V ~ 5.5 V
- Voltage - VCCB:
- 0.9 V ~ 5.5 V
- Input Signal:
- -
- Output Signal:
- -
- Output Type:
- Tri-State
- Data Rate:
- 250Mbps
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Features:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-TSSOP (0.173", 4.40mm Width)
NXU0304PWJ FAQ
1.How can I place an order for NXU0304PWJ through Aetrix?
Please submit a Request for Quotation (RFQ) for NXU0304PWJ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NXU0304PWJ reliable?
The price and inventory of NXU0304PWJ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NXU0304PWJ is usually 5 days.
3.What payment methods are accepted for NXU0304PWJ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NXU0304PWJ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NXU0304PWJ?
NXU0304PWJ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NXU0304PWJ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NXU0304PWJ?
For technical support, including NXU0304PWJ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NXU0304PWJ requirements.
6.How does Aetrix verify that NXU0304PWJ is sourced from the original manufacturer or authorized distributors?
All NXU0304PWJ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NXU0304PWJ meets industry standards.
7.What is the process for return or replacement of NXU0304PWJ?
All NXU0304PWJ units undergo pre-shipment inspection (PSI). If there is an issue with NXU0304PWJ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NXU0304PWJ part is unused and in its original packaging.
Return procedure for NXU0304PWJ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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