NXP Semiconductors OM5577/PN7120SM

Overview

PN7120SM from NXP Semiconductors is a fully integrated NFC controller IC with embedded ARM Cortex-M0 core and preloaded NCI 1.0-compliant firmware, supporting ISO/IEC 14443-A/B, ISO/IEC 15693, FeliCa, MIFARE Classic/DESFire, and NFC Forum Tag Types 1–4 in Reader, Card Emulation, and P2P modes at 13.56 MHz. It operates from 2.3 V to 5.5 V, consumes only 150 μA in low-power polling loop (500 ms), and interfaces via I²C up to 3.4 MBaud - enabling rapid NFC integration in battery-powered Linux/Android devices.

For engineers reviewing the PN7120SM datasheet, PN7120SM pinout, PN7120SM application, or PN7120SM equivalent, this page delivers verified technical context, validated pin functions, real-world power-state behavior, confirmed RF protocol coverage, and precise alternative part comparisons - all grounded in NXP's official Rev. 3.5 product data sheet and hardware design guides.

Technical Context

The PN7120SM implements an NCI 1.0 host interface over I²C with programmable slave address (0x50/0x51 or 0x52/0x53), supports clock request signaling (CLK_REQ), and features autonomous wake-up via RF field detection, internal 380 kHz timer, or I²C activity. Its RF front-end integrates a high-sensitivity demodulator, buffered antenna drivers (TX1/TX2), and RF level detector for small-form-factor antenna operation.

It embeds a dedicated power management unit enabling four distinct power states: Hard Power Down (≤12 μA), Standby (≤20 μA), Monitor (≤12 μA), and Active - with configurable polling loop sequencing across ISO/IEC 14443-A/B, FeliCa, and ISO/IEC 15693 technologies. The device uses either a 27.12 MHz crystal (XTAL1/XTAL2) or PLL-based clock synthesis from 13–52 MHz external sources.

Key Specifications

Pinout & Package

VFBGA49 package (SOT1320-1), 4.0 × 4.0 × 0.5 mm, 0.4 mm pitch - optimized for space-constrained portable and wearable designs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar NFC controller applications.

Compared with ST25DV04K, PN7120SM provides full reader/emulation/P2P capability with zero-host protocol burden; compared with PN7150, it offers proven maturity and broader ecosystem support but lacks extended temp rating and marginal power reduction.

Availability

PN7120SM is available at Aetrix Electronics and suitable for smart home gateways, wearable health monitors, Linux-based set-top boxes, industrial printers, and NFC-enabled remote controls requiring stable component supply across multi-year production cycles.

Supply support for PN7120SM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in NFC, RFID, and secure element technologies.

The PN7120SM belongs to NXP's PN71xx NFC controller family, designed specifically to accelerate NFC adoption in resource-constrained, battery-powered consumer and industrial devices through integrated firmware, ultra-low-power operation, and simplified host integration.

FAQ

What is the minimum VBAT voltage required for PN7120SM to operate in Card Emulation mode?

The PN7120SM requires a minimum VBAT of 2.3 V for Card Emulation (Target) mode, as specified in Table 1 of the Rev. 3.5 datasheet. Below this threshold, the device enters Monitor state to prevent battery deep discharge. Operation at 2.3 V is supported across the full ambient temperature range (−30°C to +85°C), enabling reliable use with aging or low-voltage batteries in wearables and remote controls.

Does PN7120SM support MIFARE Classic encryption natively, or does the host processor handle it?

PN7120SM natively supports MIFARE Classic 1K/4K encryption in PCD mode via its integrated firmware - no host-side cryptographic processing is required. The firmware implements the proprietary Crypto1 algorithm and handles authentication, key management, and sector access transparently through standard NCI commands, reducing host CPU load and eliminating security-critical software implementation.

Can PN7120SM be used without an external 27.12 MHz crystal?

Yes - PN7120SM supports both external 27.12 MHz crystal (via XTAL1/XTAL2) and PLL-based clock synthesis from 13/19.2/24/26/38.4/52 MHz reference clocks. When using PLL mode, the external clock must meet phase noise (≤−140 dBc/Hz @ 50 kHz) and accuracy (±25 ppm for 13/26/52 MHz) requirements per Table 13 to maintain RF compliance.

How does PN7120SM achieve 150 μA average current in polling loop mode?

PN7120SM achieves 150 μA average current by alternating between ultra-low-power Standby state (≤20 μA) during 500 ms listening phases and brief Active-state Poller bursts only when RF field presence is detected. This intelligent duty cycling - managed autonomously by on-chip firmware without host intervention - minimizes active time while maintaining sub-second detection latency.

Is PN7120SM pin-compatible with PN7150 for drop-in replacement?

Yes - PN7120SM and PN7150 share identical VFBGA49 (SOT1320-1) packaging, pin assignment, and power sequencing. All critical signals (VBAT, VDD(TX), IRQ, I2C, ANT1/ANT2, TX1/TX2) map 1:1, enabling mechanical and electrical drop-in replacement. Firmware migration requires only minor NCI parameter updates due to enhanced oscillator stability and power optimizations in PN7150.