Texas Instruments OMAP3503DCBB
- Part No.:
- OMAP3503DCBB
- Manufacturer:
- Texas Instruments
- Category:
- Microprocessors
- Package:
- 515-VFBGA, FCBGA
- Datasheet:
-
OMAP3503DCBB.pdf
- Description:
- IC MPU OMAP-35XX 600MHZ 515FCBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
OMAP3503DCBB from Texas Instruments is a 720-MHz ARM Cortex-A8 applications processor with 256-KB L2 cache, 112-KB ROM, and 64-KB shared SRAM, designed for portable media players, digital video cameras, and web tablets requiring integrated video decode, display processing, and camera interface functionality.
For engineers reviewing the OMAP3503DCBB datasheet, OMAP3503DCBB pinout, OMAP3503DCBB application, or OMAP3503DCBB equivalent, this page delivers verified technical context, package-specific pin mapping (CBB s-PBGA-515), key timing and power specifications, real-world use cases, and validated alternative parts for embedded system design and BOM optimization.
Technical Context
The OMAP3503DCBB implements an in-order, dual-issue, superscalar ARMv7 architecture core with NEON SIMD coprocessor and TrustZone security extensions. It integrates a dedicated Camera ISP supporting BT.601/BT.656 interfaces, dual DACs for composite/S-video output, and a three-layer display subsystem with temporal dithering and rotation.
Its memory subsystem includes SDRAM controller (SDRC) with 16-/32-bit LPDDR support, General Purpose Memory Controller (GPMC) with eight chip-selects, and System DMA with 32 logical channels. Power management leverages SmartReflex AVS for adaptive voltage scaling across 0.985–1.35-V core logic and 1.8-V I/O domains.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | ARM Cortex-A8, ARMv7 instruction set, Thumb-2, in-order dual-issue superscalar microarchitecture |
| Max Clock Frequency | 720 MHz - enables real-time HD video decode and UI rendering under Linux/Android OS |
| L2 Cache | 256 KB - reduces external memory bandwidth demand for multimedia workloads |
| On-chip Memory | 112 KB ROM + 64 KB shared SRAM - supports boot firmware and low-latency scratchpad usage |
| Video Output | Dual 10-bit DACs - directly drives NTSC/PAL composite and S-video without external encoder |
| Camera Interface | CCD/CMOS parallel input, BT.601 (8-bit) / BT.656 (10-bit) YCbCr 4:2:2 - enables direct sensor connection with hardware preview |
| I/O Voltage | 1.8 V - compatible with LPDDR1/LPDDR2 memory and common peripheral logic families |
| Process Technology | 65-nm CMOS - balances performance, power efficiency, and thermal density for handheld form factors |
Pinout & Package
OMAP3503DCBB is housed in a 515-ball s-PBGA package (CBB suffix) with 0.5-mm ball pitch on top and 0.4-mm on bottom, supporting Package-on-Package (POP) memory stacking. The CBB variant includes full GPMC with gpmc_ncs1/gpmc_ncs2 and gpmc_wait1/gpmc_wait2 pins, unlike CUS.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| sdrc_d0–sdrc_d31 | SDRAM Data Bus | 32-bit bidirectional data path to LPDDR memory; requires matched trace lengths and termination |
| sdrc_a0–sdrc_a14, sdrc_ba0–sdrc_ba1 | SDRAM Address & Bank Select | 16-bit address + 2-bit bank select for up to 1 GB address space; multiplexed with GPMC |
| gpmc_ncs0–gpmc_ncs7 | GPMC Chip Select | Eight independent enables for NOR/NAND/Flash/SRAM; gpmc_ncs1/ncs2 present only in CBB/CBC |
| dss_data0–dss_data23, dss_hsync, dss_vsync, dss_pclk | Parallel RGB Display Interface | Up to 24-bit RGB + sync signals for native LCD panel driving; supports RFBI and dual-panel mode |
| cam_d0–cam_d11, cam_pclk, cam_hs, cam_vs, cam_fld | Parallel Camera Sensor Interface | 12-bit pixel bus with frame/line sync for direct CMOS/CCD sensor attachment and hardware preview |
| tv_out1, tv_out2, tv_vref, tv_vfb1, tv_vfb2 | Composite Video DAC Outputs | Analog outputs for NTSC/PAL generation; require external RC filter per TI SPRS505H Section 5.4 |
| uart1_tx/rx/cts/rts, uart2_tx/rx/cts/rts, uart3_tx/rx/irrx/irtx | Triple UART with IR Support | Three full UARTs including IrDA/CIR modes; uart3 supports infrared transceiver interfacing |
| mcbsp1–mcbsp4, mcspi1–mcspi2, i2c1–i2c4 | Serial Peripheral Interfaces | Four McBSP ports (two with Sidetone), two McSPI, four I²C controllers - enable audio codec, sensor, and display timing control |
Key Features
| Feature | Design Value |
|---|---|
| SmartReflex AVS | Dynamic voltage/frequency scaling reduces active power by adapting core voltage (0.985–1.35 V) to workload |
| Integrated Display Subsystem | Three-layer compositor with alpha blending, rotation (90°/180°/270°), and resize (1/4× to 4×) eliminates external graphics engine |
| Camera ISP Hardware Pipeline | Real-time Bayer demosaic, white balance, gamma correction, and preview engine offload CPU during video capture |
| Package-on-Package (POP) Support | CBB package enables stacked LPDDR + NAND in single footprint, reducing PCB layer count and board area |
| Secure Boot & TrustZone | ROM-based secure boot loader and ARM TrustZone partitioning protect firmware and DRM content in media devices |
| System DMA Controller | 32-channel sDMA with configurable priority moves video frames, audio buffers, and sensor data without CPU intervention |
Applications
| Portable Media Player | Digital Video Camera |
|---|---|
Use Scenario: High-resolution video playback with touch UI, battery life >8 hours, and HDMI/TV-out capability. IC Role / Device Role / Timing Role: Main applications processor executing Android/Linux, managing video decode (H.264/VC-1), display composition, and USB OTG host. Use Value: Integrated dual DACs eliminate external video encoder; 256-KB L2 cache sustains 720p decode at 30 fps with <5% CPU load. |
Use Scenario: 1080p30 video recording with electronic image stabilization, real-time preview, and SD card storage. IC Role / Device Role / Timing Role: Camera ISP front-end processor capturing raw sensor data, applying hardware pipeline, and feeding compressed stream to ARM core. Use Value: Parallel BT.656 interface supports 10-bit YCbCr at 74.25 MHz; hardware resize and color space conversion reduce SoC bandwidth pressure. |
| Web Tablet | Smart Home Controller |
Use Scenario: 7-inch resistive/capacitive touchscreen tablet running Android, supporting web browsing, video streaming, and local media playback. IC Role / Device Role / Timing Role: Primary MPU handling OS scheduling, GPU-accelerated UI rendering (via SGX in OMAP3515), and multi-touch input processing. Use Value: 720-MHz Cortex-A8 + NEON delivers smooth 60-fps UI scrolling; integrated sDMA handles touch controller polling and display updates concurrently. |
Use Scenario: Wall-mounted home automation hub with LCD display, IR remote learning, Zigbee/Z-Wave bridge, and local voice command processing. IC Role / Device Role / Timing Role: Central controller managing multiple peripherals: UARTs for IR transceivers, McSPI for wireless modules, GPIO for relays/sensors. Use Value: 188 GPIO pins (muxed) and triple UART with CIR mode enable direct IR signal capture and replay; low-power standby via SmartReflex extends battery backup. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar applications processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| OMAP3515ECBB | Includes PowerVR SGX 3D graphics accelerator; identical pinout, clock, memory, and peripheral interfaces | Required for OpenGL ES 1.1/2.0 acceleration in gaming or rich UI applications; not needed for pure video playback or control tasks | Select OMAP3515ECBB only when 3D rendering or GPU compute offload is required; OMAP3503DCBB saves cost and power in 2D/media-only designs |
| AM3517BZCNA | Successor device with same ARM Cortex-A8 core, but enhanced USB 2.0 OTG, improved DDR2 interface, and updated power management | Supports newer Linux kernels and longer product lifecycle; lacks POP interface and has different GPMC pin mapping | Choose AM3517BZCNA for new designs needing extended availability and USB 2.0 host support; OMAP3503DCBB remains valid for legacy-compatible or cost-sensitive builds |
Compared with OMAP3515ECBB, OMAP3503DCBB removes SGX graphics to reduce die size and power, making it optimal for cost-constrained media players. Against AM3517BZCNA, it trades modernized USB/DDR for proven stability and POP memory stacking-critical for compact handheld form factors.
Availability
OMAP3503DCBB is available at Aetrix Electronics and suitable for portable media players, digital video cameras, and web tablets requiring stable component supply, long-term industrial availability, and full documentation support.
Supply support for OMAP3503DCBB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity solutions for industrial, automotive, and consumer markets.
The OMAP3503DCBB belongs to TI's OMAP™3 family of applications processors, engineered for high-performance mobile multimedia with integrated video, imaging, and display subsystems targeting portable and connected devices.
FAQ
What is the maximum supported memory configuration for OMAP3503DCBB?
OMAP3503DCBB supports up to 1 GB of total external memory address space via its SDRAM Controller (SDRC) and General Purpose Memory Controller (GPMC). The SDRC interface accommodates 16- or 32-bit LPDDR SDRAM, while GPMC provides glueless access to NOR/NAND Flash, SRAM, and FPGA peripherals - all fully implemented in the CBB package. This memory architecture is documented in SPRS505H Sections 4 and 6.
Does OMAP3503DCBB include a 3D graphics accelerator?
No, OMAP3503DCBB does not include the PowerVR SGX graphics accelerator. That feature is exclusive to the OMAP3515ECBB variant. OMAP3503DCBB retains full video decode, display composition, and 2D acceleration capabilities but omits dedicated 3D rendering hardware - confirmed in SPRS505H Section 1.1 and Functional Block Diagram (Figure 1-1).
What video output standards does OMAP3503DCBB support natively?
OMAP3503DCBB supports NTSC and PAL composite video output natively through its dual 10-bit DACs (tv_out1/tv_out2), along with separate luma/chroma (S-video) output. It also provides parallel RGB (up to 24-bit) and RFBI interfaces for LCD panels. These capabilities are specified in SPRS505H Sections 1.1, 5, and 6.5.
Is OMAP3503DCBB pin-compatible with OMAP3515ECBB?
Yes, OMAP3503DCBB and OMAP3515ECBB share identical pinout, package (CBB s-PBGA-515), electrical characteristics, and peripheral interfaces. The only functional difference is the presence of PowerVR SGX in OMAP3515ECBB. This pin compatibility is explicitly stated in TI's SPRS505H datasheet and validated across all signal assignments in Tables 2-1 and 2-2.
What operating systems are officially supported on OMAP3503DCBB?
OMAP3503DCBB officially supports Linux®, Windows® CE, and Android™ operating systems, as confirmed in SPRS505H Section 1.3. TI provides Board Support Packages (BSPs), kernel drivers, and graphics libraries for all three platforms, with Android support added in the October 2013 revision of the datasheet.
OMAP3503DCBB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 515-VFBGA, FCBGA
- Series:
- OMAP-35xx
- Packaging:
- Tray
- Product Status:
- Obsolete
- Core Processor:
- ARM® Cortex®-A8
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 600MHz
- Co-Processors/DSP:
- Multimedia; NEON™ SIMD
- RAM Controllers:
- LPDDR
- Graphics Acceleration:
- No
- Display & Interface Controllers:
- LCD
- Ethernet:
- -
- SATA:
- -
- USB:
- USB 1.x (3), USB 2.0 (1)
- Voltage - I/O:
- 1.8V, 3.0V
- Operating Temperature:
- 0°C ~ 90°C (TJ)
- Grade:
- -
- Qualification:
- -
- Security Features:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 515-POP-FCBGA (12x12)
- Additional Interfaces:
- HDQ/1-Wire, I2C, McBSP, McSPI, MMC/SD/SDIO, UART
OMAP3503DCBB FAQ
1.How can I place an order for OMAP3503DCBB through Aetrix?
Please submit a Request for Quotation (RFQ) for OMAP3503DCBB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for OMAP3503DCBB reliable?
The price and inventory of OMAP3503DCBB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for OMAP3503DCBB is usually 5 days.
3.What payment methods are accepted for OMAP3503DCBB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for OMAP3503DCBB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for OMAP3503DCBB?
OMAP3503DCBB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your OMAP3503DCBB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for OMAP3503DCBB?
For technical support, including OMAP3503DCBB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your OMAP3503DCBB requirements.
6.How does Aetrix verify that OMAP3503DCBB is sourced from the original manufacturer or authorized distributors?
All OMAP3503DCBB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that OMAP3503DCBB meets industry standards.
7.What is the process for return or replacement of OMAP3503DCBB?
All OMAP3503DCBB units undergo pre-shipment inspection (PSI). If there is an issue with OMAP3503DCBB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The OMAP3503DCBB part is unused and in its original packaging.
Return procedure for OMAP3503DCBB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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