Texas Instruments OMAPL132DZWTA2

Overview

OMAPL132DZWTA2 from Texas Instruments is a dual-core C6000™ DSP + ARM® applications processor integrating a 200-MHz ARM926EJ-S RISC MPU and a 200-MHz C674x fixed- and floating-point VLIW DSP. It delivers 1600 MIPS and 1200 MFLOPS, features 488KB on-chip RAM (including 256KB L2 unified RAM/cache), and supports DDR2/mDDR, EMIFA, USB 2.0 OTG, and 10/100 Ethernet - deployed in industrial portable navigation and smart grid substation protection systems.

For engineers reviewing the OMAPL132DZWTA2 datasheet, OMAPL132DZWTA2 pinout, OMAPL132DZWTA2 application, or OMAPL132DZWTA2 equivalent, key selection criteria include dual-core deterministic real-time processing, secure boot (AES-128/SHA-256), 128KB shared RAM for inter-processor communication, eHRPWM/eCAP timing peripherals, and PRUSS programmable real-time subsystem for offloading deterministic I/O tasks.

Technical Context

The OMAPL132DZWTA2 implements a tightly coupled heterogeneous architecture: the ARM926EJ-S core handles OS services, UI, and protocol stacks using its 16KB I-cache/16KB D-cache and MMU, while the C674x DSP executes compute-intensive signal processing with IEEE SP/DP floating-point support, 64 general-purpose registers, and dual multiply units enabling up to two SP×SP→SP operations per cycle.

Memory coherency is managed via shared 128KB SRAM and configurable L2 partitioning; peripheral access is coordinated through a high-performance switch fabric supporting EDMA3 (64 independent channels), dual McBSPs, McASP with 16 serializers, and PRUSS with two 32-bit RISC cores (4KB IRAM + 512B DRAM each) for hardware-timed GPIO, PWM, or custom protocol handling without CPU intervention.

Key Specifications

Pinout & Package

OMAPL132DZWTA2 is housed in a 361-ball Pb-free NFBGA (ZWT package) with 0.80-mm ball pitch and 16.0 mm × 16.0 mm body size. The package supports 1.2-V core and 1.8-V/3.3-V I/O operation, with dedicated power/ground ball arrays for noise-sensitive analog and digital domains.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core DSP+ARM applications.

Compared with OMAPL132DZWTA2, OMAPL138DZWTA2 offers higher clock speed and doubled L2 RAM for compute-bound workloads, while AM1808BZWT removes the DSP entirely to reduce BOM cost and power consumption - both maintain identical footprint, I/O compatibility, and software toolchain support.

Availability

OMAPL132DZWTA2 is available at Aetrix Electronics and suitable for industrial portable navigation devices, smart grid substation protection systems, biometric identification terminals, and professional mobile radio infrastructure requiring stable component supply across extended product lifecycles.

Supply support for OMAPL132DZWTA2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, delivering analog and embedded processing solutions for industrial, automotive, and communications markets since 1930.

The OMAP-L132 product line was designed for cost-sensitive, low-power industrial edge devices requiring deterministic real-time processing, secure firmware execution, and rich connectivity - bridging the gap between microcontrollers and high-end application processors.

FAQ

What is the maximum operating frequency of the ARM926EJ-S and C674x cores in OMAPL132DZWTA2?

The OMAPL132DZWTA2 integrates a 200-MHz ARM926EJ-S RISC processor and a 200-MHz C674x VLIW DSP core. Both operate at this rated frequency under recommended 1.2-V core supply and junction temperature conditions. This fixed-frequency specification is defined in the SPRS762E datasheet revision January 2017 and applies specifically to the OMAPL132DZWTA2 variant - not to higher-speed derivatives like OMAPL138DZWTA2.

Does OMAPL132DZWTA2 support secure boot, and what cryptographic algorithms are implemented?

Yes, OMAPL132DZWTA2 implements TI's Basic Secure Boot with hardware-enforced AES-128 encryption and SHA-1 or SHA-256 validation of boot images. The device uses a NIST-800-22 certified random number generator to derive a unique 128-bit cipher key, ensuring that encrypted firmware images can only be decrypted and authenticated by the target OMAPL132DZWTA2 unit - protecting intellectual property and preventing unauthorized code execution.

What external memory types does OMAPL132DZWTA2 support, and how are they interfaced?

OMAPL132DZWTA2 supports DDR2 SDRAM (16-bit, up to 156 MHz), mobile DDR (16-bit, up to 150 MHz), and asynchronous memories via EMIFA - including 8-/16-bit NOR flash, NAND flash, and 16-bit SDRAM. DDR2/mDDR connects through a dedicated high-speed controller with MRS register programming; EMIFA provides glueless interface to legacy parallel memories with configurable wait states and burst modes - both controllers are fully integrated and require no external logic.

Can the PRUSS on OMAPL132DZWTA2 be used independently of the ARM and DSP cores?

Yes, the Programmable Real-Time Unit Subsystem (PRUSS) on OMAPL132DZWTA2 consists of two independent 32-bit RISC cores, each with dedicated 4KB instruction RAM and 512 bytes of data RAM. It operates autonomously with its own clock domain and interrupt controller, and can be enabled or disabled via software without affecting ARM or DSP operation - enabling deterministic, low-latency I/O handling such as encoder counting or custom serial protocol generation without CPU scheduling delays.

What is the function of the 128KB shared RAM in OMAPL132DZWTA2, and how is it accessed?

The 128KB shared RAM in OMAPL132DZWTA2 is a dedicated on-chip SRAM block accessible by the ARM926EJ-S, C674x DSP, and EDMA3 controller via the internal switch fabric - without consuming L2 bandwidth. It serves as a zero-latency inter-processor communication buffer for passing sensor data, control commands, or processed results between ARM and DSP domains, and is mapped into both ARM and DSP address spaces at fixed physical addresses defined in the memory map.