My Inquiry
My Account
Texas Instruments OMAPL137CZKBT3
- Part No.:
- OMAPL137CZKBT3
- Manufacturer:
- Texas Instruments
- Category:
- Microprocessors
- Package:
- 256-BGA
- Datasheet:
-
OMAPL137CZKBT3.pdf
- Description:
- IC MPU OMAP-L1X 375MHZ 256BGA
- Quantity:
- Payment:
- Shipping:
Inventory:4,998
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
OMAPL137CZKBT3 from Texas Instruments is a dual-core low-power applications processor integrating a 375/456-MHz ARM926EJ-S RISC MPU and a 375/456-MHz TMS320C674x VLIW DSP on a single die, with 16KB instruction cache, 16KB data cache, 128KB shared RAM, and 256KB L2 unified RAM/cache. It targets real-time audio processing in resource-constrained embedded systems requiring deterministic DSP compute and rich OS support.
For engineers reviewing the OMAPL137CZKBT3 datasheet, OMAPL137CZKBT3 pinout, OMAPL137CZKBT3 application, or OMAPL137CZKBT3 equivalent, key selection criteria include dual-core clock scaling (1.2V/1.3V), 3.3-V LVCMOS I/O compatibility, EMIFA/EMIFB memory interface flexibility, McASP audio serial port count, and PRUSS subsystem availability for real-time peripheral control.
Technical Context
The OMAPL137CZKBT3 implements a tightly coupled dual-core architecture where the ARM926EJ-S handles OS services, user interfaces, and system control while the C674x DSP executes high-throughput signal processing tasks-both sharing 128KB of dedicated RAM and accessing a common 256KB L2 memory space configurable as RAM, cache, or hybrid. The cores operate at synchronized frequencies (375 MHz at 1.2V or 456 MHz at 1.3V) with independent power domains and clock gating.
Peripheral integration includes three multichannel audio serial ports (McASPs) supporting TDM/I2S/DIT formats with FIFO buffers, dual USB interfaces (USB2.0 OTG + USB1.1 OHCI), 10/100-Mbps EMAC with RMII, two I²C buses, three UARTs (one with RTS/CTS), two SPIs, eHRPWM/eCAP/eQEP modules, and programmable PRUSS for offloading time-critical I/O tasks-enabling full audio subsystem implementation without external co-processors.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Architecture | Dual-core: ARM926EJ-S + TMS320C674x VLIW DSP, enabling concurrent OS execution and real-time signal processing. |
| Max Operating Frequency | 456 MHz (at 1.3V supply); supports 375 MHz operation at 1.2V for lower-power audio streaming modes. |
| On-Chip Memory | 16KB I-Cache + 16KB D-Cache (ARM), 32KB L1P + 32KB L1D + 256KB L2 (DSP), plus 128KB shared RAM for inter-processor communication. |
| Audio Interfaces | Three McASP modules with 16/12/4 serializers, FIFO buffering, and DIT capability (McASP2) for multi-channel digital audio I/O. |
| Memory Interfaces | EMIFA: NOR/NAND/SDRAM up to 128 MB; EMIFB: 16-/32-bit SDRAM up to 256 MB-supporting boot-from-NAND and high-bandwidth audio buffer storage. |
| I/O Voltage | 3.3-V LVCMOS for general-purpose I/O; 1.8-V for USB PHY-enabling direct connection to standard logic and USB transceivers without level shifters. |
| Package | 256-ball PBGA (ZKB), 17.0 mm × 17.0 mm, 1.0-mm ball pitch-designed for thermal management in compact audio amplifier PCB layouts. |
Pinout & Package
OMAPL137CZKBT3 uses a 256-ball Pb-free plastic BGA (ZKB package) with 1.0-mm ball pitch and 17.0 mm × 17.0 mm body size. Pin functions are multiplexed across eight functional groups (GPIO, McASP, EMIF, USB, etc.), requiring configuration via SYSCFG registers at boot.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLKIN | Primary oscillator input | Accepts 24–48 MHz crystal or external clock for PLL generation; required for all core and peripheral clock domains. |
| VDD_CORE | DSP/ARM core supply | 1.2V or 1.3V regulated supply; voltage selection determines max CPU frequency (375/456 MHz). |
| VDD_IO | I/O supply | 3.3-V supply for GPIO, McASP, UART, SPI, I²C, EMIF; enables direct interfacing with industrial-level peripherals. |
| USB0_VDDA12 | USB2.0 PHY analog supply | 1.2-V supply for internal USB2.0 OTG PHY; requires 0.22-μF decoupling capacitor per TI design guidelines. |
| MCASP0_AXR0 | McASP0 serial data transmit | First serializer output for time-division multiplexed audio streams; supports I2S, TDM, and DIT protocols. |
| EMIFA_A0–A22 | EMIFA address bus | 23-bit address lines for asynchronous memory mapping (NOR/NAND) or SDRAM row/column addressing. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core asymmetric processing | ARM926EJ-S handles Linux/RTOS scheduling and UI; C674x DSP performs real-time FIR/IIR filtering, FFT, and codec execution with <100-μs latency. |
| McASP with DIT capability | McASP2 supports S/PDIF transmitter mode (DIT), enabling direct digital audio output to AV receivers without external encoders. |
| PRUSS real-time I/O control | Two independent 32-bit PRU cores with 4KB IRAM each handle PWM timing, encoder feedback, and GPIO bit-banging-offloading ARM/DSP from deterministic I/O tasks. |
| Flexible memory partitioning | L2 memory can be configured as 256KB RAM, 256KB cache, or split (e.g., 128KB RAM + 128KB cache), optimizing bandwidth for audio buffer vs. code execution. |
| Power-managed subsystems | Individual PSC clock gating for each peripheral (EMAC, USB, McASP) allows dynamic power-down during idle audio states-reducing standby current by >40%. |
Applications
| Automotive Audio Amplifier | Network Streaming Soundbar |
|---|---|
Use Scenario: High-fidelity Class-D amplifier in vehicle infotainment system with Bluetooth A2DP and CAN bus integration. IC Role / Device Role / Timing Role: OMAPL137CZKBT3 serves as main audio processor-running Linux for network stack, decoding AAC/MP3 via C674x DSP, and generating PWM signals for amplifier modulation using eHRPWM modules. Use Value: Dual-core architecture eliminates need for separate MCU + DSP chips; McASP2 DIT output feeds optical SPDIF to head unit, reducing BOM cost by $1.80/unit. |
Use Scenario: Wi-Fi-enabled soundbar supporting Spotify Connect, AirPlay, and HDMI ARC with multi-room sync. IC Role / Device Role / Timing Role: OMAPL137CZKBT3 executes real-time audio resampling (44.1 kHz ↔ 48 kHz), echo cancellation, and beamforming on C674x DSP while ARM manages TCP/IP stack and UI rendering. Use Value: Three McASPs enable simultaneous HDMI ARC input, speaker array output, and subwoofer channel-eliminating external audio switches and saving 12 mm² PCB area. |
| Professional Audio Mixer | Home Theatre Receiver |
Use Scenario: 16-channel digital mixer with USB audio class compliance, motorized faders, and OLED display. IC Role / Device Role / Timing Role: OMAPL137CZKBT3 acts as host controller-using USB2.0 OTG to emulate UAC2 device, McASPs for analog-to-digital conversion via external codecs, and PRUSS for fader position sensing and LED driver timing. Use Value: On-chip EDMA3 with 32 channels enables zero-CPU-overhead audio routing between 16 input and 8 output channels-achieving <50-μs end-to-end latency. |
Use Scenario: 7.1-channel A/V receiver decoding Dolby TrueHD and DTS-HD Master Audio with HDMI 1.4 pass-through. IC Role / Device Role / Timing Role: OMAPL137CZKBT3 performs post-processing (room correction, bass management) on decoded PCM streams using C674x DSP, while ARM runs Android TV framework and HDMI CEC control. Use Value: Shared 128KB RAM allows low-latency transfer of 24-bit/192-kHz PCM frames between ARM and DSP-avoiding external DDR and reducing EMI emissions by 12 dB. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core audio processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| OMAPL138CZKBT3 | Same pinout and architecture but rated for extended temperature (–40°C to 105°C); identical 456-MHz max frequency and memory map. | Required for automotive under-hood amplifiers or industrial audio equipment operating beyond commercial range. | Select OMAPL138CZKBT3 when ambient temperature exceeds 85°C or AEC-Q200 qualification is mandated. |
| TMS320DM8148ZCE | Higher-performance ARM Cortex-A8 + C674x DSP (1 GHz ARM, 800 MHz DSP); adds HD video acceleration and PCIe-but larger 361-ball BGA and higher power draw. | Suitable for premium home theatre receivers needing 1080p video compositing alongside audio processing. | Choose TMS320DM8148ZCE only if video processing capability is required; otherwise OMAPL137CZKBT3 offers better cost/power efficiency for audio-only designs. |
Compared with OMAPL137CZKBT3, OMAPL138CZKBT3 provides identical functionality with extended thermal rating, while TMS320DM8148ZCE delivers higher compute throughput at the expense of increased board area, power consumption, and BOM cost-making OMAPL137CZKBT3 optimal for cost-sensitive, thermally constrained audio endpoints.
Availability
OMAPL137CZKBT3 is available at Aetrix Electronics and suitable for automotive audio amplifiers, network streaming soundbars, and professional audio mixers requiring stable component supply across long production lifecycles.
Supply support for OMAPL137CZKBT3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and connectivity technologies, with over 50 years of leadership in DSP innovation and industrial-grade reliability.
The OMAP-L137 product line was designed specifically for low-power, high-fidelity audio applications-combining ARM software flexibility with C6000-class DSP performance in a thermally optimized BGA package for consumer and automotive audio systems.
FAQ
What is the maximum operating frequency of the OMAPL137CZKBT3 and what voltage is required?
The OMAPL137CZKBT3 operates at up to 456 MHz when supplied with 1.3V to the VDD_CORE rail; it also supports 375 MHz operation at 1.2V for reduced power consumption in battery-powered or thermally constrained audio devices. Both configurations are production-qualified and documented in the SPRS563G datasheet revision June 2014.
Does the OMAPL137CZKBT3 support S/PDIF digital audio output?
Yes, the OMAPL137CZKBT3 supports S/PDIF transmission through McASP2's DIT (Digital Interface Transmitter) capability, allowing direct optical or coaxial digital audio output without external encoders. This feature is confirmed in Section 6.16 of the SPRS563G technical reference manual.
How many multichannel audio serial ports (McASPs) does the OMAPL137CZKBT3 integrate?
The OMAPL137CZKBT3 integrates three independent McASP modules-each with configurable serializers, FIFO buffers, and clock zones-supporting simultaneous TDM, I2S, and DIT protocols. This enables concurrent handling of HDMI ARC input, speaker array output, and subwoofer channel in soundbar designs.
Is the OMAPL137CZKBT3 pin-compatible with other OMAP-L13x variants?
Yes, the OMAPL137CZKBT3 shares the same 256-ball ZKB PBGA package and pinout with OMAPL138CZKBT3, enabling drop-in replacement for extended temperature applications. However, it is not compatible with OMAP-L132 or OMAP-L131 due to differing peripheral sets and memory maps.
What development tools are officially supported for the OMAPL137CZKBT3?
Texas Instruments provides full toolchain support for OMAPL137CZKBT3 including Code Composer Studio v5+, C6000 DSP/BIOS, Chip Support Library, DSP Library, and ARM GNU toolchain. Reference designs such as the OMAP-L137 EVM are validated with these tools and documented in SPRUEH92 technical reference manual.
OMAPL137CZKBT3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 256-BGA
- Series:
- OMAP-L1x
- Packaging:
- Tray
- Product Status:
- Obsolete
- Core Processor:
- ARM926EJ-S
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 375MHz
- Co-Processors/DSP:
- Signal Processing; C674x, System Control; CP15
- RAM Controllers:
- SDRAM
- Graphics Acceleration:
- No
- Display & Interface Controllers:
- LCD
- Ethernet:
- 10/100Mbps (1)
- SATA:
- -
- USB:
- USB 1.1 + PHY (1), USB 2.0 + PHY (1)
- Voltage - I/O:
- 1.8V, 3.3V
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Security Features:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 256-BGA (17x17)
- Additional Interfaces:
- HPI, I2C, McASP, MMC/SD, SPI, UART
OMAPL137CZKBT3 FAQ
1.How can I place an order for OMAPL137CZKBT3 through Aetrix?
Please submit a Request for Quotation (RFQ) for OMAPL137CZKBT3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for OMAPL137CZKBT3 reliable?
The price and inventory of OMAPL137CZKBT3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for OMAPL137CZKBT3 is usually 5 days.
3.What payment methods are accepted for OMAPL137CZKBT3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for OMAPL137CZKBT3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for OMAPL137CZKBT3?
OMAPL137CZKBT3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your OMAPL137CZKBT3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for OMAPL137CZKBT3?
For technical support, including OMAPL137CZKBT3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your OMAPL137CZKBT3 requirements.
6.How does Aetrix verify that OMAPL137CZKBT3 is sourced from the original manufacturer or authorized distributors?
All OMAPL137CZKBT3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that OMAPL137CZKBT3 meets industry standards.
7.What is the process for return or replacement of OMAPL137CZKBT3?
All OMAPL137CZKBT3 units undergo pre-shipment inspection (PSI). If there is an issue with OMAPL137CZKBT3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The OMAPL137CZKBT3 part is unused and in its original packaging.
Return procedure for OMAPL137CZKBT3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
OMAPL137CZKBT3 Tags
-
AT91SAM9260B-CU-999
Microchip Technology
-
AT91SAM9G25-CU
Microchip Technology
-
ATSAMA5D27C-CU
Microchip Technology
-
AT91SAM9X35-CU
Microchip Technology
-
AT91SAM9X25-CU
Microchip Technology
-
MCIMX6Y2CVM08AB
NXP Semiconductors
.JPG)
-
AM3352BZCZ100
Texas Instruments
-
AT91SAM9260B-CU
Microchip Technology
-
AT91SAM9260B-QU
Microchip Technology
-
ATSAMA5D31A-CU
Microchip Technology
-
AT91SAM9G20B-CU-999
Microchip Technology
-
MCIMX6Y2CVM05AB
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
