Texas Instruments OMAPL138EZCEA3

Overview

OMAPL138EZCEA3 from Texas Instruments is a dual-core C6000™ DSP + ARM® SoC integrating a 456-MHz ARM926EJ-S RISC processor and a 456-MHz C674x VLIW DSP core, with 256KB L2 unified RAM/cache, 128KB shared RAM, and 1.8-V/3.3-V LVCMOS I/Os. It targets industrial portable navigation, smart grid substation protection, and biometric identification systems requiring real-time signal processing and embedded OS support.

For engineers reviewing the OMAPL138EZCEA3 datasheet, OMAPL138EZCEA3 pinout, OMAPL138EZCEA3 application, or OMAPL138EZCEA3 equivalent, key selection criteria include dual-core clock synchronization, DDR2/mDDR memory controller timing compliance, EMAC MII/RMII interface configuration, and PRUSS subsystem programmability for deterministic I/O offload.

Technical Context

The OMAPL138EZCEA3 implements tightly coupled ARM926EJ-S and C674x cores sharing a 256KB L2 memory space configurable as RAM, cache, or mixed mode, while maintaining separate 32KB L1P/L1D caches per core. Its EDMA3 controller supports 64 independent DMA channels with programmable burst sizes for zero-copy data movement between peripherals like McASP, McBSP, and uPP.

Peripheral coherency is managed via a switched central resource (SCR) and pin multiplexing controlled by SYSCFG registers. The device uses a single PLL/clock generator with integrated oscillator to derive core, peripheral, and interface clocks-including dedicated USB PHY clocks, SATA reference clocks, and RTC 32-kHz oscillator input-enabling synchronized multi-domain operation without external clock distribution.

Key Specifications

Pinout & Package

OMAPL138EZCEA3 is housed in a 361-ball NFBGA (ZCE) package with 0.65-mm ball pitch and 13.0 mm × 13.0 mm body size. Pin assignments follow TI's standardized OMAP-L138 ZCE ball map, where power, ground, and high-speed interfaces (DDR2, EMAC, USB) are distributed across dedicated banks to minimize noise coupling.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core DSP+ARM applications.

Compared with OMAPL138ZCEA3, the OMAPL138EZCEA3 provides guaranteed operation across –40°C to 105°C for ruggedized deployments, while AM1808ZCE03 eliminates DSP capability entirely-making it unsuitable for applications requiring real-time FFT, filtering, or modulation that depend on C674x VLIW execution.

Availability

OMAPL138EZCEA3 is available at Aetrix Electronics and suitable for industrial portable navigation devices, smart grid substation protection relays, and biometric identification terminals requiring stable component supply across extended temperature ranges and long product lifecycles.

Supply support for OMAPL138EZCEA3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, delivering analog and embedded processing solutions for industrial, automotive, and communications markets.

The OMAP-L138 product line was designed for cost-sensitive, low-power industrial applications requiring integrated DSP acceleration and full-featured ARM application processing in a single chip-targeting smart grid, portable instrumentation, and real-time vision systems.

FAQ

What is the maximum operating frequency of the OMAPL138EZCEA3 ARM926EJ-S and C674x cores?

The OMAPL138EZCEA3 operates both its ARM926EJ-S and C674x cores at 456 MHz under 1.3-V core supply conditions. This frequency is validated across the extended temperature range (–40°C to 105°C) and requires adherence to TI's recommended power sequencing and decoupling guidelines specified in the SPRS586J datasheet Section 5.3.

Does the OMAPL138EZCEA3 support secure boot, and what cryptographic algorithms are used?

Yes, the OMAPL138EZCEA3 implements TI Basic Secure Boot using AES-128 for boot image encryption and SHA-256 for image authentication. The secure boot flow starts from a hardware root-of-trust, encrypts boot modules stored in external flash, and validates them during load-ensuring that only authenticated, unmodified firmware executes on the OMAPL138EZCEA3.

What memory interfaces does the OMAPL138EZCEA3 provide, and what are their maximum supported densities?

The OMAPL138EZCEA3 integrates two memory controllers: an EMIFA supporting 128-MB address space for NOR/NAND/SDRAM, and a DDR2/mDDR controller supporting 256-MB address space for 16-bit DDR2 or mobile DDR SDRAM. Both interfaces are electrically and timing-validated per JEDEC standards and require layout compliance with TI's ZCE package routing guidelines.

Can the OMAPL138EZCEA3's PRUSS be used to implement custom communication protocols without CPU involvement?

Yes, the OMAPL138EZCEA3's Programmable Real-Time Unit Subsystem (PRUSS) contains two independent 32-bit RISC PRU cores, each with dedicated 4KB instruction RAM and 512B data RAM. These cores execute autonomously, allowing implementation of bit-banged UART, SPI, or proprietary serial protocols with microsecond-level timing precision-freeing the ARM9 and C674x cores for higher-layer tasks.

What is the function of the 128KB shared RAM in the OMAPL138EZCEA3, and how is it accessed?

The 128KB shared RAM in the OMAPL138EZCEA3 is a dedicated on-chip memory block accessible by both the ARM926EJ-S and C674x cores, as well as the EDMA3 controller, without contention against the DSP's 256KB L2 memory. It is mapped into the system address space at 0xC0000000 and used for zero-copy inter-processor communication, buffer staging, and real-time data exchange-critical for deterministic latency in applications like biometric matching or motor control.