Texas Instruments OMAPL138EZCEA3E

Overview

OMAPL138EZCEA3E from Texas Instruments is a dual-core C6000™ DSP + ARM® SoC integrating a 456-MHz ARM926EJ-S RISC MPU and a 456-MHz C674x VLIW DSP, with 256KB L2 unified RAM/cache, 128KB shared RAM, and 1.8-V/3.3-V LVCMOS I/Os. It targets industrial portable navigation, smart grid substation protection, and biometric identification systems requiring deterministic real-time signal processing and robust OS support.

For engineers reviewing the OMAPL138EZCEA3E datasheet, OMAPL138EZCEA3E pinout, OMAPL138EZCEA3E application, or OMAPL138EZCEA3E equivalent, key selection criteria include dual-core clock synchronization, DDR2/mDDR memory controller timing compliance, EMAC MII/RMII interface configuration, and PRUSS subsystem power-gating behavior in low-power modes.

Technical Context

The OMAPL138EZCEA3E implements tightly coupled ARM926EJ-S and C674x cores sharing a 128KB dedicated SRAM and accessing a unified 256KB L2 memory space configurable as RAM, cache, or mixed. Its EDMA3 controller features two channel controllers and 64 independent DMA channels for zero-overhead data movement between peripherals and L2 or DDR2.

Peripheral integration includes a USB 2.0 OTG port with integrated PHY, SATA I/II controller with hardware-assisted NCQ (32-entry), and a programmable PRUSS with two 32-bit RISC cores-each with 4KB instruction RAM and 512B data RAM-operating under a single PSC clock-gating domain for deterministic latency control.

Key Specifications

Pinout & Package

OMAPL138EZCEA3E uses a 361-ball NFBGA package (ZCE suffix) with 13.0 mm × 13.0 mm body size and 0.65-mm ball pitch, compliant with JEDEC MO-275AB standard. Thermal resistance θ_JA is 29.5°C/W (JEDEC High-K board).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core DSP+ARM applications.

Compared with OMAPL138ZCEA3, OMAPL138EZCEA3E adds extended temperature qualification essential for uncontrolled environments; compared with AM1808ZCE3, it retains full C674x DSP capability enabling standalone signal processing without host CPU intervention.

Availability

OMAPL138EZCEA3E is available at Aetrix Electronics and suitable for industrial portable navigation devices, smart grid substation protection relays, and biometric identification terminals requiring stable component supply across extended temperature ranges and long product lifecycles.

Supply support for OMAPL138EZCEA3E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, delivering analog and embedded processing solutions for industrial, automotive, and communications markets.

The OMAP-L138 product line was designed for cost-sensitive, low-power industrial applications requiring both general-purpose processing (ARM) and high-performance signal processing (DSP) in a single chip - targeting smart grid, portable instrumentation, and machine vision edge nodes.

FAQ

What is the maximum DDR2 data rate supported by OMAPL138EZCEA3E?

OMAPL138EZCEA3E supports DDR2 SDRAM at up to 156 MHz clock frequency, enabling 312 MT/s effective data rate on its 16-bit bus. This is confirmed in Section 3.1 of the SPRS586J datasheet under "DDR2/mDDR Memory Controller" specifications and validated by timing parameters in Table 6-11 for t_RP, t_RCD, and t_RC at 156 MHz operation. The DDR2 controller is fully integrated and requires no external PHY.

Does OMAPL138EZCEA3E include hardware encryption acceleration beyond secure boot?

No, OMAPL138EZCEA3E does not include dedicated cryptographic accelerators (e.g., AES, SHA, RSA engines). Its security functionality is limited to TI Basic Secure Boot using on-chip AES-128 and SHA-256 for boot image decryption and validation. All runtime encryption/decryption must be performed in software on the ARM or DSP cores, as confirmed in the Security User's Guide (SPRUGN2) and absence of crypto peripherals in the functional block diagram.

Can the PRUSS in OMAPL138EZCEA3E access DDR2 memory directly?

Yes, the PRUSS in OMAPL138EZCEA3E can access DDR2 memory directly via the system interconnect - the PRU cores are connected to the L3 interconnect through the Switched Central Resource (SCR), granting them full visibility into the entire memory map including DDR2 address space. This is documented in Section 6.33 of SPRS586J and verified by PRU assembly examples using L3 address offsets for DDR2 reads/writes.

What is the function of the ZCE suffix in OMAPL138EZCEA3E?

The ZCE suffix in OMAPL138EZCEA3E denotes the 361-ball NFBGA package with 13.0 mm × 13.0 mm body size and 0.65-mm ball pitch, as defined in TI's device nomenclature (Section 7.1 of SPRS586J). It distinguishes this variant from the ZWT package (16 mm × 16 mm, 0.80-mm pitch) and confirms mechanical compatibility with existing ZCE-footprint PCBs.

Is OMAPL138EZCEA3E pin-compatible with OMAPL138ZCEA3?

Yes, OMAPL138EZCEA3E is pin-compatible with OMAPL138ZCEA3 - both use the identical ZCE package (361-ball NFBGA, 0.65-mm pitch) and share the same ball map, electrical characteristics, and thermal profile. The only differences are temperature grade (extended −40°C to +105°C vs. commercial 0°C to +90°C) and internal speed binning confirmation, as stated in TI's packaging documentation (SPRS693).