Texas Instruments OMAPL138EZCEA3R

Overview

OMAPL138EZCEA3R from Texas Instruments is a dual-core C674x DSP + ARM926EJ-S applications processor in a 361-ball NFBGA (0.65-mm pitch, 13×13 mm), operating at 375 MHz with 32KB L1P/L1D cache, 256KB L2 unified RAM/cache, and 128KB shared RAM. It integrates EMAC, USB 2.0 OTG + USB 1.1 OHCI, SATA I/II, McASP, VPIF, PRUSS, and eHRPWM/eCAP peripherals for real-time embedded signal processing and control.

For engineers reviewing the OMAPL138EZCEA3R datasheet, OMAPL138EZCEA3R pinout, OMAPL138EZCEA3R application, or OMAPL138EZCEA3R equivalent, key selection criteria include dual-core clock synchronization, DDR2/mDDR memory controller timing compliance, secure boot (AES-128/SHA-256), and peripheral coexistence constraints such as USB0/USB1 multiplexing and VPIF capture/display channel allocation.

Technical Context

The OMAPL138EZCEA3R implements tightly coupled ARM926EJ-S and C674x cores sharing L2 and 128KB RAM, with independent cache hierarchies (16KB I/D cache for ARM; 32KB L1P/L1D + 256KB L2 for DSP) and EDMA3-managed data movement across subsystems. Its memory architecture supports simultaneous ARM code execution and DSP algorithm acceleration without bus contention.

Peripheral integration follows a hierarchical bus structure: AHB for high-speed ARM-side access (EMAC, USB, SATA), crossbar for DSP-side peripherals (McASP, McBSP, uPP), and dedicated PRUSS interconnect for deterministic real-time I/O. All clocks derive from configurable PLLs with independent domain gating, enabling dynamic voltage/frequency scaling per core.

Key Specifications

Pinout & Package

OMAPL138EZCEA3R uses a 361-ball Pb-free plastic ball grid array (PBGA) package with 0.65-mm ball pitch and 13.0 mm × 13.0 mm body size. The package supports industrial temperature range (–40°C to 85°C) and requires controlled impedance routing for DDR2, USB, and McASP interfaces.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core DSP+ARM applications.

Compared with OMAPL138ZCEA3, OMAPL138EZCEA3R adds Pb-free compliance and industrial temperature rating; compared with AM1808ZCE3, it provides integrated C674x DSP, VPIF, SATA, and PRUSS-enabling self-contained video, storage, and real-time I/O without external components.

Availability

OMAPL138EZCEA3R is available at Aetrix Electronics and suitable for industrial motor control, smart grid protection relays, machine vision edge analyzers, and professional radio baseband processing requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for OMAPL138EZCEA3R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, designing analog, embedded processing, and wireless chips for industrial, automotive, and communications markets.

The OMAP-L138 product line targets low-power, cost-sensitive embedded systems requiring both general-purpose OS capability and real-time DSP acceleration-specifically for industrial automation, energy infrastructure, and portable professional audio/video equipment.

FAQ

What is the maximum supported DDR2 clock frequency for OMAPL138EZCEA3R?

The OMAPL138EZCEA3R DDR2 memory controller supports up to 156 MHz (312 MT/s data rate) for 16-bit DDR2 SDRAM, delivering 624 MB/s peak bandwidth. This frequency is validated under industrial temperature conditions with proper termination and layout adherence to JEDEC DDR2-333/400 specifications, and requires VDD_DDR = 1.8V ± 3%.

Does OMAPL138EZCEA3R support secure boot with customer-defined keys?

Yes, OMAPL138EZCEA3R implements TI Basic Secure Boot using AES-128 for image encryption and SHA-256 for signature validation. Customers generate and inject their own private keys during manufacturing; the device-specific 128-bit cipher key is generated internally via NIST-800-22 certified RNG and never exposed, ensuring cryptographic isolation of each unit's key hierarchy.

Can OMAPL138EZCEA3R simultaneously operate USB 2.0 OTG and USB 1.1 OHCI interfaces?

No, OMAPL138EZCEA3R cannot operate USB0 (OTG) and USB1 (OHCI) concurrently due to shared PHY resources and pin multiplexing constraints documented in Section 3.7 of the datasheet. When USB0 is active, USB1 pins are reassigned to other functions; system design must choose one USB mode per configuration.

What is the role of the PRU subsystem in OMAPL138EZCEA3R real-time applications?

The PRU subsystem in OMAPL138EZCEA3R consists of two independent 32-bit RISC cores with dedicated 4KB instruction RAM and 512B data RAM each, enabling microsecond-deterministic I/O handling. It directly controls eHRPWM, eCAP, GPIO, and UART peripherals without ARM/DSP intervention-critical for motor commutation timing, encoder quadrature decoding, and custom protocol bit-banging in industrial motion control.

How does OMAPL138EZCEA3R manage memory coherency between ARM and DSP subsystems?

OMAPL138EZCEA3R uses explicit software-managed cache coherency: ARM and DSP maintain separate L1 caches (16KB/32KB), while shared L2 and 128KB RAM are cacheable only when configured as non-cacheable regions or accessed via cache-clean/invalidate instructions. EDMA3 transfers bypass caches entirely, ensuring deterministic data movement without hardware snoop overhead.