Texas Instruments OMAPL138EZWTA3

Overview

OMAPL138EZWTA3 from Texas Instruments is a dual-core C6000™ DSP + ARM® SoC integrating a 456-MHz ARM926EJ-S RISC processor and a 456-MHz C674x VLIW DSP core, with 256KB L2 unified RAM/cache, 128KB shared RAM, and integrated peripherals including EMAC, USB 2.0 OTG, SATA I/II, McASP, and PRUSS - deployed in industrial automation, remote radio units, and smart grid protection systems.

For engineers reviewing the OMAPL138EZWTA3 datasheet, OMAPL138EZWTA3 pinout, OMAPL138EZWTA3 application, or OMAPL138EZWTA3 equivalent, key selection criteria include dual-core clock synchronization, DDR2/mDDR memory controller timing, secure boot (AES-128/SHA-256), and peripheral multiplexing constraints across 361-ball PBGA package variants.

Technical Context

The OMAPL138EZWTA3 implements tightly coupled ARM926EJ-S and C674x cores sharing L2 and 128KB RAM, with independent cache hierarchies (16KB I/D-cache for ARM; 32KB L1P/L1D for DSP) and EDMA3-based data movement. Its memory subsystem supports concurrent access via AHB/EMIF buses while enforcing MMU-based memory protection and TLB-managed virtual addressing.

Peripherals are partitioned into fixed-function (EMAC, USB OTG/OHCI, SATA) and configurable subsystems (PRUSS with two 32-bit RISC cores, eHRPWM/eCAP timers, uPP parallel interface), all synchronized to multiple PLL-derived clocks and managed by a centralized Power/Sleep Controller (PSC) with domain-level clock gating.

Key Specifications

Pinout & Package

OMAPL138EZWTA3 is housed in a 361-ball NFBGA (ZWT) package with 0.80-mm ball pitch and 16.0 mm × 16.0 mm body size. Pin assignments follow TI's OMAP-L138 ZWT mechanical layout, where ball rows A–V and columns 1–19 define terminal functions per multiplexing group.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core DSP+ARM applications.

Compared with OMAPL138CZCEA3 and AM1808BZWT4, the OMAPL138EZWTA3 uniquely delivers full C674x DSP compute capability alongside ARM9 in the ZWT package, enabling mixed-workload applications requiring both rich OS services and high-throughput signal processing without external accelerators.

Availability

OMAPL138EZWTA3 is available at Aetrix Electronics and suitable for industrial automation, remote radio units, and smart grid protection systems requiring stable component supply across extended product lifecycles.

Supply support for OMAPL138EZWTA3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, delivering analog and embedded processing solutions for industrial, automotive, and communications markets.

The OMAP-L138 product line targets cost-sensitive, low-power embedded applications requiring heterogeneous processing - combining ARM application control with C6000 DSP compute for real-time signal, video, and communication workloads.

FAQ

What is the maximum operating frequency of the OMAPL138EZWTA3?

The OMAPL138EZWTA3 operates at a maximum frequency of 456 MHz for both its ARM926EJ-S and C674x DSP cores, achieved at 1.3-V core voltage. This rating is validated across the industrial temperature range (–40°C to +85°C) and requires compliance with TI's recommended power-on hours and thermal derating curves per SPRS586J Section 5.3.

Does the OMAPL138EZWTA3 support secure boot, and what cryptographic algorithms are used?

Yes, the OMAPL138EZWTA3 implements TI Basic Secure Boot using AES-128 for image encryption and SHA-256 for signature validation. The boot ROM enforces hardware-based authentication before loading any user code, and the JTAG interface remains locked until explicitly enabled during development - ensuring that OMAPL138EZWTA3 deployments meet foundational security requirements for protected firmware execution.

What memory interfaces does the OMAPL138EZWTA3 provide, and what are their supported configurations?

The OMAPL138EZWTA3 integrates two independent memory controllers: an EMIFA supporting 8-/16-bit NOR/NAND flash and 16-bit SDRAM, and a DDR2/mDDR controller supporting 16-bit wide DDR2 (up to 156 MHz) or mobile DDR (up to 150 MHz) with 256-MB address space. Both interfaces are accessible to ARM, DSP, and EDMA3, with L2 and 128KB shared RAM providing low-latency inter-processor data exchange without bus arbitration delays.

How many PRU cores does the OMAPL138EZWTA3 include, and what resources are allocated per core?

The OMAPL138EZWTA3 includes two independent Programmable Real-Time Unit (PRU) cores within its PRUSS subsystem. Each PRU core has 4KB of instruction RAM and 512 bytes of data RAM, supports 32-bit load-store RISC execution, and exports register R30 externally for system-level synchronization - enabling OMAPL138EZWTA3 to handle time-critical I/O tasks such as encoder counting, PWM generation, or protocol bridging without ARM or DSP intervention.

What is the package type and ball pitch of the OMAPL138EZWTA3?

The OMAPL138EZWTA3 uses a 361-ball NFBGA package with ZWT suffix, measuring 16.0 mm × 16.0 mm with 0.80-mm ball pitch. This package variant offers improved thermal dissipation over the smaller ZCE variant and is mechanically and electrically compatible with TI's OMAP-L138 reference designs and evaluation modules, including the OMAP-L138 EVM.