Texas Instruments OMAPL138EZWTA3E

Overview

OMAPL138EZWTA3E from Texas Instruments is a dual-core C6000™ DSP + ARM® SoC integrating a 456-MHz ARM926EJ-S RISC MPU and a 456-MHz C674x VLIW DSP, with 256KB L2 unified RAM/cache, 128KB shared RAM, and 1.8-/3.3-V LVCMOS I/Os - deployed in industrial portable navigation, smart grid substation protection, and biometric identification systems.

For engineers reviewing the OMAPL138EZWTA3E datasheet, OMAPL138EZWTA3E pinout, OMAPL138EZWTA3E application, or OMAPL138EZWTA3E equivalent, key selection considerations include dual-core clock synchronization, DDR2/mDDR memory controller timing compliance, EMAC MII/RMII interface configuration, and PRUSS real-time peripheral offload capability.

Technical Context

The OMAPL138EZWTA3E implements a tightly coupled ARM926EJ-S and C674x DSP subsystem sharing L2 memory and EDMA3 resources, with independent cache hierarchies (16KB I-cache/16KB D-cache for ARM; 32KB L1P/32KB L1D for DSP) and hardware-assisted cache coherency management. Its memory architecture supports concurrent access to 256KB L2 RAM/cache and 128KB dedicated shared RAM without performance contention.

Peripheral interconnect uses a multi-layer AHB/AXI fabric enabling simultaneous high-bandwidth transfers across EMAC, SATA, uPP, and VPIF - with programmable pin multiplexing allowing dynamic allocation of 361-ball PBGA terminals between McASP, McBSP, USB OTG/Host, and dual SPI/MMC interfaces under system-level timing constraints.

Key Specifications

Pinout & Package

OMAPL138EZWTA3E is housed in a 361-ball NFBGA package (ZWT suffix) with 16.0 mm × 16.0 mm body size and 0.80-mm ball pitch, compliant with JEDEC MO-256. Thermal pad exposed on underside requires solder paste stencil design per TI SZZA031.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core DSP+ARM applications.

Compared with OMAPL138EZWTA3E, OMAPL138CZCEA3 trades 21% lower clock rate and smaller package for reduced thermal design complexity, while AM3358BZCZ100 abandons DSP hardware entirely in favor of higher single-thread ARM performance and broader Linux driver support - making it viable only where C674x-specific algorithms are absent.

Availability

OMAPL138EZWTA3E is available at Aetrix Electronics and suitable for industrial portable navigation devices, smart grid substation protection IEDs, and biometric identification terminals requiring stable component supply across extended product lifecycles.

Supply support for OMAPL138EZWTA3E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, delivering analog and embedded processing solutions for industrial, automotive, and communications markets since 1930.

The OMAP-L138 product line was engineered to bridge high-performance DSP computation with ARM-based OS capabilities in resource-constrained industrial edge devices - targeting applications demanding both real-time signal processing and rich user interfaces.

FAQ

What is the maximum operating frequency of the OMAPL138EZWTA3E and what voltage is required?

The OMAPL138EZWTA3E operates at a maximum frequency of 456 MHz for both its ARM926EJ-S and C674x DSP cores, requiring a 1.3V ±3% core supply (VDD_CORE) as specified in the SPRS586J datasheet Section 5.3. This voltage level is mandatory to sustain 456-MHz operation; using 1.2V limits maximum frequency to 375 MHz. The OMAPL138EZWTA3E's power management unit dynamically adjusts core voltage during DVFS transitions to maintain stability.

Does the OMAPL138EZWTA3E support secure boot, and what cryptographic algorithms are implemented?

Yes, the OMAPL138EZWTA3E implements TI Basic Secure Boot using AES-128 for boot image encryption and SHA-256 for image authentication, as documented in the TMS320C674x/OMAP-L1x Processor Security User's Guide. The secure boot flow begins from a hardware root-of-trust, locks JTAG by default, and decrypts/authenticates images loaded from external NAND or SPI flash. OMAPL138EZWTA3E does not support RSA or ECC-based signature verification - only symmetric AES/SHA primitives.

What memory interfaces are available on the OMAPL138EZWTA3E and how are they allocated?

The OMAPL138EZWTA3E integrates two independent memory controllers: a DDR2/mDDR controller supporting 16-bit bus width and 256MB address space, and an EMIFA supporting 8/16-bit NOR/NAND flash and 16-bit SDRAM. These interfaces are electrically isolated and managed by separate AHB masters. The OMAPL138EZWTA3E also includes 256KB of on-chip L2 RAM/cache and 128KB of dedicated shared RAM - all accessible without arbitration delay.

How does the PRUSS subsystem in the OMAPL138EZWTA3E differ from standard microcontroller peripherals?

The PRUSS in the OMAPL138EZWTA3E contains two independent 32-bit RISC cores (PRU0/PRU1), each with 4KB instruction RAM and 512B data RAM, executing at full core clock speed without cache or MMU - enabling sub-microsecond I/O response. Unlike standard peripherals, PRUSS exposes register R30 for direct ARM-DSP-PRU handshaking and supports real-time GPIO, PWM, and encoder functions without CPU scheduling. OMAPL138EZWTA3E's PRUSS is disabled by default and must be enabled via PSC registers.

What USB configurations does the OMAPL138EZWTA3E support and are external PHYs required?

The OMAPL138EZWTA3E integrates two USB PHYs: a USB 2.0 OTG PHY (USB0) supporting high/full/low-speed device/host modes, and a USB 1.1 OHCI PHY (USB1) for full-speed host-only operation. No external PHYs are required - both interfaces use internal transceivers with on-die termination. The OMAPL138EZWTA3E's USB0 port complies with USB 2.0 specification and supports up to four endpoints (control, bulk, interrupt, isochronous) with hardware-assisted descriptor handling.