Texas Instruments OMAPL138EZWTD4E

Overview

OMAPL138EZWTD4E from Texas Instruments is a dual-core C6000™ DSP + ARM® SoC integrating a 456-MHz ARM926EJ-S RISC MPU and a 456-MHz C674x VLIW DSP, with 256KB L2 unified RAM/cache, 128KB shared RAM, and 1.3-V core voltage. It delivers 2746 MFLOPS and 3648 MIPS for real-time signal processing and embedded control in industrial and communications systems.

For engineers reviewing the OMAPL138EZWTD4E datasheet, OMAPL138EZWTD4E pinout, OMAPL138EZWTD4E application, or OMAPL138EZWTD4E equivalent, key selection criteria include dual-core clock synchronization, DDR2/mDDR memory controller timing, EMAC+MDIO Ethernet interface configuration, and PRUSS real-time I/O co-processing capability.

Technical Context

The OMAPL138EZWTD4E implements tightly coupled ARM926EJ-S and C674x cores sharing a unified memory map, with separate 16KB instruction and data caches for ARM and 32KB L1P/L1D for DSP. Its EDMA3 subsystem supports 64 independent DMA channels across two channel controllers, enabling zero-copy data movement between peripherals like McASP, McBSP, and EMAC.

Real-time determinism is enhanced by the Programmable Real-Time Unit Subsystem (PRUSS), featuring two 32-bit RISC PRU cores with 4KB instruction RAM and 512B data RAM each, directly accessible via dedicated interrupt controller and switched central resource - independent of ARM/DSP execution flow.

Key Specifications

Pinout & Package

OMAPL138EZWTD4E uses a 361-ball NFBGA package (ZWT suffix) with 0.80-mm ball pitch and 16.0 mm × 16.0 mm body size. Pin assignment follows TI's OMAP-L138 ZWT pinout specification (SPRS586J, Section 3.6), supporting multiplexed functions across 9 GPIO banks, dual McASP/McBSP, and dedicated high-speed interfaces including uPP, VPIF, and SATA.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core DSP+ARM applications.

Compared with OMAPL138EZWTD4E, OMAPL138ZCEA offers identical functionality in a smaller footprint but demands higher PCB fabrication precision, while AM1808AZWT sacrifices DSP compute and real-time I/O (PRUSS, McASP) for lower cost and power in non-signal-intensive roles.

Availability

OMAPL138EZWTD4E is available at Aetrix Electronics and suitable for industrial automation PLCs, remote radio heads, smart grid protection relays, and biometric identification terminals requiring stable component supply across extended product lifecycles.

Supply support for OMAPL138EZWTD4E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, delivering analog and embedded processing solutions for industrial, automotive, and communications markets.

The OMAP-L138 product line was designed for cost-sensitive, low-power embedded applications demanding both general-purpose OS support (ARM) and real-time signal processing (DSP), targeting industrial control, communications infrastructure, and intelligent sensing.

FAQ

What is the maximum operating frequency of the OMAPL138EZWTD4E?

The OMAPL138EZWTD4E operates at a maximum frequency of 456 MHz for both the ARM926EJ-S core and the C674x DSP core, achieved at 1.3-V core supply voltage per TI SPRS586J revision January 2017. This frequency is factory-configured and not user-overclockable; thermal and voltage margins must be maintained per recommended operating conditions.

Does the OMAPL138EZWTD4E support secure boot, and what cryptographic algorithms does it use?

Yes, the OMAPL138EZWTD4E implements TI Basic Secure Boot using AES-128 for boot image encryption and SHA-1 or SHA-256 for image authentication. The process starts from a hardware root-of-trust in ROM, locks JTAG by default, and decrypts/authenticates code loaded from external flash or EEPROM before execution - ensuring OMAPL138EZWTD4E firmware integrity and intellectual property protection.

What memory interfaces are integrated into the OMAPL138EZWTD4E?

The OMAPL138EZWTD4E integrates two independent external memory interfaces: an asynchronous EMIFA supporting NOR/NAND flash and 16-bit SDRAM, and a high-speed DDR2/mDDR controller supporting 16-bit wide 256-MB address space at up to 156 MHz (DDR2) or 150 MHz (mDDR). It also includes 256KB L2 unified RAM/cache and 128KB dedicated shared RAM.

Can the OMAPL138EZWTD4E execute both ARM and DSP code simultaneously, and how is inter-processor communication handled?

Yes, the OMAPL138EZWTD4E supports true concurrent execution of ARM and DSP code via its dual-core architecture. Inter-processor communication is implemented through shared memory (128KB RAM and L2), hardware semaphores, and the EDMA3 controller for zero-copy data transfer. No software mailbox or polling is required - the OMAPL138EZWTD4E provides direct memory access and interrupt signaling between cores.

What is the role of the PRUSS in the OMAPL138EZWTD4E, and how does it differ from the ARM and DSP cores?

The Programmable Real-Time Unit Subsystem (PRUSS) in the OMAPL138EZWTD4E consists of two independent 32-bit RISC PRU cores with dedicated 4KB instruction RAM and 512B data RAM each. Unlike the ARM and DSP, PRUSS executes time-critical, low-latency tasks (e.g., PWM generation, encoder counting, custom protocol handling) without OS scheduling or cache interference - providing deterministic sub-microsecond response that complements OMAPL138EZWTD4E's main processors.