Texas Instruments ONET8551TYS9
- Part No.:
- ONET8551TYS9
- Manufacturer:
- Texas Instruments
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- Die
- Datasheet:
-
ONET8551TYS9.pdf
- Description:
- IC TRANSIMPEDANCE 1 CIRC WAFER
- Quantity:
- Payment:

- Shipping:

Inventory:2,597
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ONET8551TYS9 from Texas Instruments is a 11.3-Gbps limiting transimpedance amplifier (TIA) optimized for optical receiver front-ends in high-speed fiber communication systems. It delivers 9-GHz bandwidth, –20-dBm sensitivity at 10.3125 Gbps, and 10-kΩ differential small-signal transimpedance, with integrated RSSI for signal strength monitoring in PIN/APD-based receivers.
For engineers reviewing the ONET8551TYS9 datasheet, ONET8551TYS9 pinout, ONET8551TYS9 application, or ONET8551TYS9 equivalent, key selection criteria include input-referred noise (0.9–1.4 μARMS), CML output compliance (on-chip 50-Ω back-termination), dual RSSI outputs (RSSI_IB/RSSI_EB), bandwidth configurability via BW0/BW1 pins, and die-level packaging for TO-can integration.
Technical Context
The ONET8551TYS9 implements a three-stage signal path: a photodiode-current-to-voltage transimpedance amplifier (TIA), a limiting voltage amplifier with automatic gain control (AGC), and a CML output buffer with on-chip 50-Ω termination to VCC. Its AGC dynamically adjusts gain to maintain limiting behavior across input currents from 25 μAP-P to 2.5 mAP-P.
Dual supply domains isolate VCC_IN (2.8–3.63 V for TIA stage) from VCC_OUT (same range for AGC/CML stages), while internal supply filtering eliminates need for external bypass capacitors. Bandwidth tuning is achieved via two digital inputs (BW0/BW1), enabling discrete adjustment between 7–9 GHz depending on grounding configuration.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Small-signal bandwidth | 7–9 GHz - determines maximum data rate support (up to 11.3 Gbps) and eye-opening integrity under real-world parasitics |
| Transimpedance gain | 10 kΩ differential - sets conversion ratio from photodiode current to usable voltage swing at amplifier output |
| Sensitivity | –20 dBm @ 10.3125 Gbps - minimum optical input power required to achieve BER ≤10–12 with PRBS31 pattern |
| Input-referred noise | 0.9–1.4 μARMS - directly limits detectable signal amplitude and impacts SNR in low-light conditions |
| Power dissipation | 92 mW typical - enables thermal management in compact TO-can packages without active cooling |
| RSSI accuracy | 0.46–0.63 A/A gain (RSSI_EB), 0.49–0.54 A/A (RSSI_IB) - enables calibrated optical power monitoring using external load resistor |
| Supply voltage range | 2.8–3.63 V - supports standard 3.3-V rail with ±10% tolerance; dual supplies allow independent optimization of TIA and output stages |
Pinout & Package
The ONET8551TYS9 is supplied as a bare die (WAFERSALE package type) with dimensions 870 μm × 1036 μm and thickness 203 ±13 μm. It requires conductive epoxy attachment to ground for back-side thermal and electrical connection.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN | Analog input | Photodiode anode connection point; accepts up to 2.5 mAP-P input current; low-capacitance layout critical for bandwidth preservation |
| OUT+, OUT– | Differential CML outputs | On-chip 50-Ω back-terminated to VCC; require AC coupling (e.g., 0.1-μF caps) to downstream logic |
| RSSI_IB, RSSI_EB | Analog current outputs | RSSI_IB used with internal PD bias; RSSI_EB for external APD/PIN bias; both sink current proportional to signal amplitude |
| VCC_IN, VCC_OUT | Independent supply rails | VCC_IN powers TIA stage only; VCC_OUT powers AGC, RSSI, and CML buffer - enables noise isolation and supply optimization |
| FILTER1, FILTER2 | Photodiode bias outputs | Regulated, filtered DC voltage (~VCC – 100 mV) for PIN diode cathode; must connect photodiode to enable internal biasing |
| BW0, BW1 | Digital bandwidth controls | Grounding either/both increases bandwidth (max 9 GHz); open = reduced bandwidth/noise trade-off |
| GND (1,3,6,10,14,16,18,19) | Supply ground | All bonded to common die ground; full bonding recommended for optimal RF performance and thermal conduction |
| NC (Pad 11) | No-connect | Must remain unconnected; no internal circuitry attached |
Key Features
| Feature | Design Value |
|---|---|
| Dual RSSI outputs | Separate RSSI_IB (for internal PD bias) and RSSI_EB (for external APD/PIN bias) enable accurate optical power monitoring across receiver architectures |
| Configurable bandwidth | BW0/BW1 pins allow discrete selection between 7 GHz (both open) and 9 GHz (both grounded), supporting noise-bandwidth trade-offs per system requirement |
| Integrated supply filtering | On-chip VCC bypass capacitors eliminate need for external bulk capacitance, simplifying TO-can layout and reducing component count |
| Independent supply domains | VCC_IN and VCC_OUT separation prevents TIA noise coupling into output stages, improving jitter and signal integrity |
| Low-input-noise design | 0.9 μARMS input-referred noise at 10 GHz enables reliable detection at –20 dBm sensitivity, meeting SONET OC-192 and 10G-EPON requirements |
Applications
| 10-Gigabit Ethernet Receivers | SONET OC-192 Optical Modules |
|---|---|
Use Scenario: High-density SFP+ transceivers operating at 10.3125 Gbps over single-mode fiber. IC Role / Device Role / Timing Role: Front-end limiting TIA converting photodiode current to clean CML data stream with embedded RSSI for link diagnostics. Use Value: –20-dBm sensitivity and 9-GHz bandwidth ensure robust operation under worst-case extinction ratio and dispersion, while RSSI enables real-time link health monitoring. | Use Scenario: Long-haul telecom line cards requiring OC-192 (9.953 Gbps) compliance with stringent BER and jitter specs. IC Role / Device Role / Timing Role: Core TIA in PIN-based receiver subassembly, providing stable transimpedance gain and deterministic jitter <24 psP-P at full rate. Use Value: Dual supply domains and on-chip filtering suppress supply-induced jitter, meeting SONET mask requirements without external decoupling complexity. |
| 10-G EPON OLT/ONU Receivers | CPRI/OBSAI Remote Radio Heads |
Use Scenario: Passive optical network equipment handling burst-mode upstream signals and continuous downstream at 10.3125 Gbps. IC Role / Device Role / Timing Role: Limiting TIA with fast AGC response and RSSI feedback for dynamic range management during burst acquisition. Use Value: 2.5-mAP-P overload capability and 30–150 kHz low-frequency bandwidth enable reliable burst-mode detection without saturation recovery delay. | Use Scenario: Fiber-fed cellular base stations using CPRI v6 (10.1376 Gbps) or OBSAI RP3-01 (10.1376 Gbps) interfaces. IC Role / Device Role / Timing Role: Analog front-end TIA in fronthaul receiver, delivering low-jitter CML output compatible with FPGA or ASIC SerDes inputs. Use Value: 92-mW power budget and die-level form factor allow integration into space-constrained RRH modules while maintaining thermal stability from –40°C to +100°C. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar limiting transimpedance amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX3748AETE+ | Lower bandwidth (4.5 GHz), fixed 5.5-kΩ transimpedance, no RSSI output, 3.3-V single supply only | Suitable for 3.125-Gbps Fibre Channel but not 10G+ protocols; lacks signal-strength monitoring | Select when cost-sensitive 4-Gbps applications require proven reliability and simpler biasing |
| LMH6525MA/NOPB | DC-coupled VGA architecture (not limiting TIA), 2-GHz bandwidth, no integrated RSSI or photodiode biasing | Used in analog baseband receivers rather than optical front-ends; requires external TIA and bias control | Choose only for non-limiting, variable-gain analog signal conditioning where optical-specific features are unnecessary |
Compared with MAX3748AETE+ and LMH6525MA/NOPB, the ONET8551TYS9 uniquely combines 9-GHz bandwidth, integrated RSSI, dual-supply isolation, and TO-can-optimized die packaging-making it the only option qualified for 10G+ optical standards like SONET OC-192 and 10G-EPON without external support circuitry.
Availability
ONET8551TYS9 is available at Aetrix Electronics and suitable for 10-Gigabit Ethernet transceivers, SONET OC-192 line cards, and CPRI fronthaul modules requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for ONET8551TYS9 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-speed interface solutions, with decades of expertise in optical communications ICs.
The ONET8551TYS9 belongs to TI's ONET family of high-speed optical receiver ICs, designed specifically for 10G-class fiber infrastructure where sensitivity, jitter, and integration density are critical.
FAQ
What is the primary function of the ONET8551TYS9 in optical receiver designs?
The ONET8551TYS9 serves as a limiting transimpedance amplifier that converts photodiode current into a clean, differential CML data stream. It provides 10-kΩ transimpedance gain, 9-GHz bandwidth, –20-dBm sensitivity, and integrated RSSI for optical power monitoring - all within a die-level package optimized for TO-can integration. The ONET8551TYS9 enables compact, high-performance front-ends for 10G+ protocols including 10G-EPON and SONET OC-192.
Does the ONET8551TYS9 support both PIN and APD photodiodes?
Yes, the ONET8551TYS9 supports both PIN and APD photodiodes through dual biasing and RSSI configurations. For PIN diodes, use FILTER1/FILTER2 outputs and RSSI_IB; for APDs with external bias, use RSSI_EB and omit internal FILTER connections. The device includes dedicated circuitry to maintain RSSI accuracy under both bias schemes, though TI recommends RSSI_IB for highest precision when internal bias is employed. This flexibility makes the ONET8551TYS9 suitable across multiple optical receiver topologies.
How does bandwidth adjustment work on the ONET8551TYS9?
Bandwidth adjustment on the ONET8551TYS9 is controlled by two digital inputs: BW0 and BW1. Grounding either pin increases bandwidth; grounding both achieves the maximum 9-GHz specification. Leaving both open reduces bandwidth to ~7 GHz, lowering noise for lower-data-rate or higher-sensitivity applications. These pins are internally pulled up to VCC, so no external pull-ups are needed. The ONET8551TYS9 datasheet specifies exact bandwidth vs. temperature and process corner under each configuration, ensuring predictable performance across manufacturing lots.
What are the supply voltage requirements for the ONET8551TYS9?
The ONET8551TYS9 requires two independent 2.8–3.63-V supplies: VCC_IN powers the transimpedance amplifier stage, and VCC_OUT powers the AGC, RSSI, and CML output buffer. This separation prevents noise coupling from output switching into the sensitive TIA input. Both rails must be regulated and low-noise; the device includes on-chip supply filtering, eliminating need for external bulk capacitors. Total typical power dissipation is 92 mW, making the ONET8551TYS9 suitable for thermally constrained TO-can packages.
Can the ONET8551TYS9 be used without connecting the RSSI outputs?
Yes, the ONET8551TYS9 operates fully without RSSI connections. RSSI_IB and RSSI_EB are optional current-output pins; leaving them open disables RSSI functionality with no impact on TIA or CML performance. If RSSI is unused, TI recommends leaving the pads unconnected (not tied to ground or VCC) to avoid unintended loading or leakage paths. The ONET8551TYS9 maintains its specified –20-dBm sensitivity, 9-GHz bandwidth, and 2.5-mAP-P overload capability regardless of RSSI usage - ensuring design flexibility across cost- and feature-sensitive applications.
ONET8551TYS9 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- Die
- Packaging:
- Tube
- Product Status:
- Active
- Amplifier Type:
- Transimpedance
- Number of Circuits:
- 1
- Output Type:
- -
- Slew Rate:
- -
- Gain Bandwidth Product:
- -
- -3db Bandwidth:
- 9 GHz
- Current - Input Bias:
- -
- Voltage - Input Offset:
- -
- Current - Supply:
- 28mA
- Current - Output / Channel:
- -
- Voltage - Supply Span (Min):
- 2.8 V
- Voltage - Supply Span (Max):
- 3.63 V
- Operating Temperature:
- -40°C ~ 100°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- Wafer
ONET8551TYS9 FAQ
1.How can I place an order for ONET8551TYS9 through Aetrix?
Please submit a Request for Quotation (RFQ) for ONET8551TYS9 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ONET8551TYS9 reliable?
The price and inventory of ONET8551TYS9 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ONET8551TYS9 is usually 5 days.
3.What payment methods are accepted for ONET8551TYS9?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ONET8551TYS9 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ONET8551TYS9?
ONET8551TYS9 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ONET8551TYS9 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ONET8551TYS9?
For technical support, including ONET8551TYS9 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ONET8551TYS9 requirements.
6.How does Aetrix verify that ONET8551TYS9 is sourced from the original manufacturer or authorized distributors?
All ONET8551TYS9 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ONET8551TYS9 meets industry standards.
7.What is the process for return or replacement of ONET8551TYS9?
All ONET8551TYS9 units undergo pre-shipment inspection (PSI). If there is an issue with ONET8551TYS9, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ONET8551TYS9 part is unused and in its original packaging.
Return procedure for ONET8551TYS9:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ONET8551TYS9 Tags

-
LM358DT
STMicroelectronics

-
LM358DR
Texas Instruments

-
LM2904DR
Texas Instruments

-
LM358ADR
Texas Instruments
-
LM2904DGKR
Texas Instruments
-
LM324DR
Texas Instruments

-
MCP6006T-E/OT
Microchip Technology

-
MCP6006UT-E/OT
Microchip Technology

-
LM324PWR
Texas Instruments

-
LM2902PWR
Texas Instruments
-
LM2902DR
Texas Instruments

-
LM358P
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

