Texas Instruments ONET9901PARGP
- Part No.:
- ONET9901PARGP
- Manufacturer:
- Texas Instruments
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 20-VFQFN Exposed Pad
- Datasheet:
-
ONET9901PARGP.pdf
- Description:
- IC LIMITING 1 CIRCUIT 20QFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,278
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Product details
Overview
ONET9901PARGP from Texas Instruments is a high-speed limiting post amplifier for optical receiver front-ends, supporting data rates up to 10.7 Gbps with 42 dB gain, 10 GHz f3dB, and loss-of-signal (LOS) detection. It delivers low-jitter differential output swing from input signals as low as 2–6 mVPP, and operates on a single 3.3-V supply in SFP/XFP optical modules.
For engineers reviewing the ONET9901PARGP datasheet, ONET9901PARGP pinout, ONET9901PARGP application, or ONET9901PARGP equivalent, key selection factors include its 10.7 Gbps bandwidth, 42 dB fixed gain, LOS functionality, 116 mW typical power consumption, and RGP package compatibility with industry-standard 4×4-mm QFN footprints.
Technical Context
The ONET9901PARGP implements a fully differential limiting amplifier architecture optimized for high-sensitivity optical receivers. Its 10 GHz small-signal bandwidth and 42 dB gain enable robust signal recovery from low-amplitude photodiode outputs while maintaining <1 ps RMS jitter at 10.7 Gbps.
It integrates a dedicated loss-of-signal (LOS) comparator with programmable threshold and hysteresis, enabling reliable link status monitoring without external circuitry. The device is characterized for operation from 0°C to 85°C - distinct from the –40°C to 85°C range of earlier ONETx1PA variants.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data rate | Up to 10.7 Gbps - supports OC-192/STM-64 and 10G Ethernet physical layer compliance |
| f3dB bandwidth | 10.0 GHz - ensures full eye opening and minimal intersymbol interference at 10.7 Gbps |
| Gain | 42 dB - provides sufficient amplification to drive CML or LVPECL logic from sub-6 mVPP inputs |
| Input dynamic range | 2–6 mVPP min to 1200 mVPP max - accommodates wide photodiode current variations without saturation |
| Power dissipation | 116 mW typical - enables thermal management in dense SFP+ and XFP module layouts |
| Supply voltage | Single 3.3 V - simplifies power delivery and eliminates need for dual-rail supplies |
| Operating temperature | 0°C to 85°C - qualified for commercial-grade optical transceiver applications |
Pinout & Package
ONET9901PARGP is housed in a 4×4-mm, 20-pin QFN package (RGP suffix), thermally enhanced with exposed thermal pad. Pin assignment follows TI's standard ONET post amplifier layout for signal integrity and impedance control.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Power supply input | 3.3-V analog/digital supply; requires local 100-nF bypass capacitor |
| GND | Ground reference | Common return for analog and digital sections; tied to thermal pad |
| INP / INN | Differential input pair | Accepts low-amplitude AC-coupled photodiode current-derived voltage (2–6 mVPP) |
| OUTP / OUTN | Differential output pair | LVPECL-compatible output swing (~800 mVPP); drives CDR or serializer directly |
| LOS | Loss-of-signal indicator | Open-drain active-low output signaling input signal below programmable threshold |
| EN | Enable control | Active-high digital input enabling/disabling amplifier operation to reduce standby power |
Key Features
| Feature | Design Value |
|---|---|
| 10.7 Gbps data-rate support | Enables use in 10G Ethernet, SONET OC-192, and SDH STM-64 optical receiver designs without retiming |
| 42 dB fixed gain | Provides consistent signal level translation across process/voltage/temperature for stable CDR lock |
| Integrated LOS detection | Eliminates need for external comparators and threshold-setting resistors in ROSA designs |
| Single 3.3-V supply operation | Reduces BOM count and PCB area versus dual-supply alternatives; compatible with common module power rails |
| 4×4-mm 20-pin QFN (RGP) | Matches footprint of competing 10G post amps; supports automated assembly and thermal via placement under pad |
Applications
| SONET/SDH Optical Modules | SFP/SFF Optical Modules |
|---|---|
Use Scenario: Line-side receiver in OC-192/STM-64 add-drop multiplexers requiring high sensitivity and jitter tolerance. IC Role / Device Role / Timing Role: Limiting post amplifier conditioning photodiode output before CDR clock recovery. Use Value: 10.7 Gbps bandwidth and 42 dB gain ensure full eye opening and BER <10−12 at –28 dBm input. | Use Scenario: Receive path in hot-pluggable SFP modules used in enterprise switches and routers. IC Role / Device Role / Timing Role: Final-stage amplification stage converting low-level photodiode signal to clean CML-compatible output. Use Value: Single 3.3-V supply and 4×4-mm QFN package enable compact, low-power ROSA integration. |
| XFP Optical Transceivers | Optical Transmission Equipment |
Use Scenario: High-density XFP modules deployed in metro DWDM systems with tight thermal constraints. IC Role / Device Role / Timing Role: High-fidelity signal restoration block after TIA, feeding multi-gigabit serializer. Use Value: 116 mW typical power and 0°C to 85°C qualification support sustained operation in sealed module housings. | Use Scenario: Central office optical line terminals requiring long-term reliability and signal integrity over temperature. IC Role / Device Role / Timing Role: Critical limiting amplifier in redundant receive paths with LOS monitoring for fault isolation. Use Value: Integrated LOS output enables real-time link health reporting without additional ICs or firmware overhead. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar post amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ONET9901PARGT | Same die, 3×3-mm 16-pin QFN (RGT) package; 100 mW lower thermal mass | Better suited for space-constrained SFF modules where board area is critical | Select RGT for smaller footprint; select RGP for improved thermal performance in XFP modules |
| MAX3765 | 10.3 Gbps max, 35 dB gain, no integrated LOS, 3.3-V supply, 20-pin QFN | Lacks LOS monitoring; requires external comparator for link status detection | Choose MAX3765 only if LOS is implemented externally and gain margin allows 7 dB shortfall |
Compared with ONET9901PARGP, ONET9901PARGT offers identical electrical performance in a smaller package but reduced thermal capacity, while MAX3765 lacks LOS and delivers 7 dB less gain - requiring careful system-level SNR budgeting.
Availability
ONET9901PARGP is available at Aetrix Electronics and suitable for SONET/SDH optical modules, SFP/SFF optical modules, and XFP transceivers requiring stable component supply, long-lifecycle support, and guaranteed traceability.
Supply support for ONET9901PARGP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company delivering analog and embedded processing solutions for industrial, automotive, and communications markets.
The ONET product line targets high-speed optical networking applications, with ONET9901PARGP specifically engineered for 10G-class limiting amplification in pluggable optical transceivers and ROSA assemblies.
FAQ
What is the operating temperature range for ONET9901PARGP?
ONET9901PARGP is characterized for operation from 0°C to 85°C, as specified in TI's official documentation for the ONET99x1PA family. This differs from earlier ONETx1PA devices rated for –40°C to 85°C. The 0°C lower limit reflects qualification for commercial-grade optical module environments, not extended industrial use. Always verify ambient and junction temperature margins in final layout for ONET9901PARGP.
Does ONET9901PARGP support loss-of-signal (LOS) detection?
Yes, ONET9901PARGP includes an integrated loss-of-signal (LOS) detector with open-drain active-low output. It monitors input signal amplitude against an internal threshold and asserts LOS when input falls below the detection window. This feature eliminates the need for external comparators in ROSA designs and is confirmed in TI's ONET9901PA product bulletin. ONET9901PARGP does not include RSSI functionality.
What package type is used by ONET9901PARGP?
ONET9901PARGP uses a 4×4-mm, 20-pin QFN package with exposed thermal pad (RGP suffix). This differs from the 3×3-mm, 16-pin QFN (RGT) variant. The RGP package provides higher thermal dissipation capability, making it suitable for XFP and other thermally demanding 10G optical modules. Pinout and thermal design guidelines are documented in TI's ONET9901PA datasheet.
How much gain does ONET9901PARGP provide, and how does it compare to other ONET post amplifiers?
ONET9901PARGP provides 42 dB of gain, which is lower than the 50 dB gain of ONET2501PA, ONET3301PA, and ONET4201PA. This reduction accommodates higher input signal levels expected in 10G optical front-ends while preserving dynamic range and minimizing distortion. The 42 dB value is fixed and confirmed in TI's comparative table for ONET9901PA and ONET9911PA.
Is ONET9901PARGP pin-compatible with ONET9901PARGT?
No, ONET9901PARGP is not pin-compatible with ONET9901PARGT. ONET9901PARGP uses a 20-pin QFN (RGP), while ONET9901PARGT uses a 16-pin QFN (RGT). The pin counts, layouts, and thermal pad configurations differ. Although both share the same die and core functionality, PCB redesign is required when substituting between RGP and RGT packages. Always consult TI's package drawings before migration.
ONET9901PARGP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 20-VFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Amplifier Type:
- Limiting
- Number of Circuits:
- 1
- Output Type:
- Differential
- Slew Rate:
- -
- Gain Bandwidth Product:
- -
- -3db Bandwidth:
- 10 GHz
- Current - Input Bias:
- -
- Voltage - Input Offset:
- -
- Current - Supply:
- 35mA
- Current - Output / Channel:
- -
- Voltage - Supply Span (Min):
- 3 V
- Voltage - Supply Span (Max):
- 3.6 V
- Operating Temperature:
- 0°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-QFN (4x4)
ONET9901PARGP FAQ
1.How can I place an order for ONET9901PARGP through Aetrix?
Please submit a Request for Quotation (RFQ) for ONET9901PARGP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ONET9901PARGP reliable?
The price and inventory of ONET9901PARGP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ONET9901PARGP is usually 5 days.
3.What payment methods are accepted for ONET9901PARGP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ONET9901PARGP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ONET9901PARGP?
ONET9901PARGP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ONET9901PARGP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ONET9901PARGP?
For technical support, including ONET9901PARGP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ONET9901PARGP requirements.
6.How does Aetrix verify that ONET9901PARGP is sourced from the original manufacturer or authorized distributors?
All ONET9901PARGP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ONET9901PARGP meets industry standards.
7.What is the process for return or replacement of ONET9901PARGP?
All ONET9901PARGP units undergo pre-shipment inspection (PSI). If there is an issue with ONET9901PARGP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ONET9901PARGP part is unused and in its original packaging.
Return procedure for ONET9901PARGP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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