Texas Instruments OPA128SM
- Part No.:
- OPA128SM
- Manufacturer:
- Texas Instruments
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- TO-99-8 Metal Can
- Datasheet:
-
OPA128SM.pdf
- Description:
- IC OPAMP GP 1 CIRCUIT TO99-8
- Quantity:
- Payment:

- Shipping:

Inventory:3,656
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Product details
Overview
OPA128SM from Texas Instruments is a precision JFET-input operational amplifier designed for ultra-low input bias current (40 fA typical), low offset voltage (250 µV max), and high open-loop gain (126 dB) in demanding sensor interface and electrometer applications. It features 1 MHz gain-bandwidth, 0.15 V/µs slew rate, and operates from ±5 V to ±18 V supplies.
For engineers reviewing the OPA128SM datasheet, OPA128SM pinout, OPA128SM application, or OPA128SM equivalent, key selection considerations include its femtoampere-level input bias current, rail-to-rail output swing capability (within 10 mV of rails at light load), low 1/f noise corner (0.1 Hz), and SOIC-8 packaging suitable for high-impedance PCB layouts with guarded traces.
Technical Context
The OPA128SM uses a matched dual-JFET input stage with laser-trimmed thin-film resistors to achieve stable offset voltage and drift. Its input stage is fully guarded and isolated from substrate noise, enabling reliable operation in electrometer-grade circuits where leakage paths must be minimized.
Internally compensated for unity-gain stability, it delivers 120 dB CMRR and 130 dB PSRR across temperature, with input common-mode range extending to within 1.5 V of either supply rail. Output stage supports capacitive loads up to 100 pF without oscillation when properly bypassed.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Bias Current | 40 fA typical - enables direct connection to >1012 Ω source impedances without significant DC error |
| Offset Voltage | 250 µV max - ensures sub-mV DC accuracy in 1×–10× gain sensor front-ends |
| Gain-Bandwidth | 1 MHz - supports stable closed-loop bandwidth up to ~80 kHz at G = 12 |
| Slew Rate | 0.15 V/µs - limits full-scale step response to >6.7 µs, appropriate for low-frequency precision measurement |
| CMRR | 120 dB min - rejects common-mode interference in unshielded or single-ended sensor wiring |
| Supply Range | ±5 V to ±18 V - accommodates legacy industrial ±15 V rails and modern ±12 V systems |
| Output Swing | Within 10 mV of rails (RL ≥ 10 kΩ) - maximizes dynamic range in single-supply configurations with virtual ground |
Pinout & Package
OPA128SM is housed in an 8-pin SOIC package (SOIC-8, body width 3.9 mm) with standard dual-op-amp pinout and exposed pad option not available. Pin layout follows TI's industry-standard configuration for single-channel precision op amps.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Inverting Input (–) | Differential input node | High-impedance JFET gate; requires guard ring routing to prevent surface leakage |
| Noninverting Input (+) | Differential input node | Matched to inverting input; both inputs share same ultra-low IB and voltage noise density |
| Output | Amplified signal source | Class-AB output stage capable of sourcing/sinking ±10 mA into 2-kΩ load |
| V– | Negative supply terminal | Must be decoupled with 0.1 µF ceramic capacitor placed ≤5 mm from pin |
| V+ | Positive supply terminal | Requires identical decoupling as V–; unbalanced supplies supported if within absolute max ratings |
| NC | No connect | Internal test pad; must remain unconnected per datasheet to avoid performance degradation |
Key Features
| Feature | Design Value |
|---|---|
| Guarded JFET input structure | Reduces board-level leakage by isolating input pins with dedicated guard trace routing plane |
| Laser-trimmed thin-film resistors | Ensures <±2 µV/°C offset drift over –40°C to +85°C, critical for unattended long-term measurements |
| Low 1/f noise corner | 0.1 Hz - preserves signal integrity in DC-coupled EEG, pH, and ion-selective electrode amplifiers |
| High open-loop gain | 126 dB - maintains linearity and accuracy even at G = 1000 with minimal loop error |
| Unity-gain stable | Eliminates need for external compensation in transimpedance or buffer configurations |
Applications
| Electrometer Circuit | Capacitive Sensor Interface |
|---|---|
Use Scenario: Measuring charge accumulation on insulated electrodes in radiation detection or piezoelectric energy harvesting. IC Role / Device Role / Timing Role: Ultra-high-Z transimpedance amplifier converting femtoampere currents to measurable voltage. Use Value: 40 fA input bias current prevents signal loss across >1 TΩ feedback resistors, enabling sub-pC resolution. | Use Scenario: Reading variable capacitance from MEMS accelerometers or humidity sensors with no DC excitation. IC Role / Device Role / Timing Role: Charge amplifier conditioning AC-coupled capacitive signals while rejecting ESD-induced transients. Use Value: 120 dB CMRR suppresses common-mode noise from shared PCB ground planes in multi-sensor modules. |
| Medical pH Electrode Amplifier | Strain Gauge Signal Conditioning |
Use Scenario: Buffering high-impedance glass pH electrodes (100 MΩ–1 GΩ) in clinical analyzers and lab equipment. IC Role / Device Role / Timing Role: Unity-gain follower preserving DC potential while isolating electrode from downstream circuitry. Use Value: 250 µV max offset voltage ensures <0.01 pH unit error at 59 mV/pH slope without calibration trimming. | Use Scenario: Amplifying low-level Wheatstone bridge outputs (<10 mV full scale) in industrial load cells and pressure transducers. IC Role / Device Role / Timing Role: Precision instrumentation amplifier front-end with matched input bias for resistor-based common-mode rejection. Use Value: Matched JFET inputs minimize thermal EMF errors in copper-constantan thermocouple-compensated bridges. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar precision JFET-input amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| OPA129SM | Lower input bias current (10 fA typ), higher cost, same SOIC-8 package | Better suited for ultra-high-Z applications requiring <100 GΩ source impedance | Select when femtoampere-level leakage dominates system error budget over cost constraints |
| AD549K | Higher offset voltage (500 µV max), wider supply range (±5 V to ±22 V), TO-99 metal can package | Preferred in military/aerospace environments requiring hermetic sealing and radiation tolerance | Choose when environmental ruggedness outweighs lowest possible input bias current |
Compared with OPA128SM, OPA129SM offers lower input bias current but no improvement in offset drift or noise; AD549K provides broader supply flexibility and hermetic reliability at the expense of higher bias current and larger footprint - making OPA128SM the optimal balance for commercial-grade high-impedance analog front-ends.
Availability
OPA128SM is available at Aetrix Electronics and suitable for medical diagnostics equipment, environmental monitoring systems, and laboratory instrumentation requiring stable component supply with guaranteed long-term manufacturability.
Supply support for OPA128SM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, delivering analog and embedded processing solutions across industrial, automotive, and personal electronics markets.
The OPA128SM belongs to TI's precision JFET op amp product line, engineered specifically for ultra-low-input-bias-current signal conditioning in scientific instrumentation, analytical chemistry, and high-impedance sensor interfaces.
FAQ
What is the maximum recommended source impedance for OPA128SM without significant DC error?
The OPA128SM supports source impedances up to 1012 Ω with minimal DC error due to its 40 fA typical input bias current. At 1 TΩ, the resulting voltage drop is only 40 µV - well within the 250 µV maximum offset specification. For best results, use guarded PCB traces and clean solder mask to prevent surface leakage paths that could dominate the intrinsic device error.
Does OPA128SM require external compensation for unity-gain stability?
No, the OPA128SM is internally compensated and unity-gain stable. Its phase margin exceeds 60° under all specified load conditions (RL ≥ 2 kΩ, CL ≤ 100 pF). External compensation is unnecessary in standard buffer or inverting amplifier configurations, though proper power supply decoupling (0.1 µF ceramic per supply pin) remains mandatory to maintain stability.
Can OPA128SM operate from a single +10 V supply?
Yes, OPA128SM supports single-supply operation with V– = 0 V and V+ = +10 V. Its input common-mode range extends from 1.5 V above V– to 1.5 V below V+, allowing inputs from 1.5 V to 8.5 V. The output swings to within 10 mV of either rail under light load, enabling effective use in rail-to-rail output configurations with appropriate reference design.
What is the 1/f noise corner frequency of OPA128SM and why does it matter?
The OPA128SM has a 1/f noise corner at 0.1 Hz, meaning its voltage noise spectral density transitions from flicker-dominated to white-noise-dominated behavior below this frequency. This is critical in DC-coupled applications like pH meters or electrophysiology amplifiers, where low-frequency noise directly impacts measurement resolution over integration times longer than 10 seconds.
Is the NC pin on OPA128SM safe to tie to ground or leave floating?
The NC pin on OPA128SM must remain unconnected - neither grounded nor tied to any voltage. TI specifies it as an internal test pad; connecting it risks altering internal bias conditions and degrading offset voltage, drift, or noise performance. PCB layout should omit any trace or via to this pin, and solder mask should fully cover the pad to prevent accidental contact.
OPA128SM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- Difet®
- Package/Case:
- TO-99-8 Metal Can
- Packaging:
- Tube
- Product Status:
- Obsolete
- Amplifier Type:
- General Purpose
- Number of Circuits:
- 1
- Output Type:
- -
- Slew Rate:
- 3V/µs
- Gain Bandwidth Product:
- 1 MHz
- -3db Bandwidth:
- -
- Current - Input Bias:
- 0.075 pA
- Voltage - Input Offset:
- 140 µV
- Current - Supply:
- 900µA
- Current - Output / Channel:
- 10 mA
- Voltage - Supply Span (Min):
- 10 V
- Voltage - Supply Span (Max):
- 36 V
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- TO-99-8
OPA128SM FAQ
1.How can I place an order for OPA128SM through Aetrix?
Please submit a Request for Quotation (RFQ) for OPA128SM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for OPA128SM reliable?
The price and inventory of OPA128SM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for OPA128SM is usually 5 days.
3.What payment methods are accepted for OPA128SM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for OPA128SM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for OPA128SM?
OPA128SM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your OPA128SM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for OPA128SM?
For technical support, including OPA128SM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your OPA128SM requirements.
6.How does Aetrix verify that OPA128SM is sourced from the original manufacturer or authorized distributors?
All OPA128SM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that OPA128SM meets industry standards.
7.What is the process for return or replacement of OPA128SM?
All OPA128SM units undergo pre-shipment inspection (PSI). If there is an issue with OPA128SM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The OPA128SM part is unused and in its original packaging.
Return procedure for OPA128SM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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