Texas Instruments OPA132UAE4
- Part No.:
- OPA132UAE4
- Manufacturer:
- Texas Instruments
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
OPA132UAE4.pdf
- Description:
- IC OPAMP GP 1 CIRCUIT 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:3,532
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
OPA132UAE4 from Texas Instruments is a single-channel, high-speed JFET-input operational amplifier designed for precision analog signal conditioning in high-impedance sensor interfaces and data acquisition systems. It delivers 8 MHz gain-bandwidth, ±20 V/µs slew rate, 8 nV/√Hz input voltage noise at 1 kHz, ±50 pA max input bias current, and operates from ±2.5 V to ±18 V supplies.
For engineers reviewing the OPA132UAE4 datasheet, OPA132UAE4 pinout, OPA132UAE4 application, or OPA132UAE4 equivalent, this page provides verified specifications, package mapping to SOIC-8, functional pin definitions, real-world use cases in SAR ADC drivers and photodiode amplifiers, and two validated alternative op-amps with documented technical and application differences.
Technical Context
The OPA132UAE4 employs a cascoded JFET input stage that maintains ultra-low input bias current (≤50 pA) across its full common-mode range (±13 V), eliminating phase reversal under overdrive - a known failure mode in legacy FET-input op-amps. Its unity-gain stable architecture supports direct use in voltage followers and active filters without external compensation.
Internally trimmed offset voltage (≤500 µV) and high open-loop gain (130 dB into 600 Ω) enable precision DC-coupled applications, while low THD+noise (0.00008% at 1 kHz) and fast settling (0.7 µs to 0.1%) support high-fidelity audio and fast data acquisition paths.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Gain-Bandwidth Product | 8 MHz - supports stable closed-loop operation up to 8× gain at 1 MHz or unity gain at 8 MHz. |
| Slew Rate | ±20 V/µs - enables clean 10 Vpp output swing at ≥500 kHz without slewing distortion. |
| Input Voltage Noise | 8 nV/√Hz at 1 kHz - critical for low-noise amplification of microvolt-level sensor signals. |
| Input Bias Current | ±50 pA max - preserves signal integrity in >1 GΩ source impedance circuits (e.g., piezoelectric sensors). |
| Supply Voltage Range | ±2.5 V to ±18 V - allows operation from low-power battery systems to industrial ±15 V rails. |
| Open-Loop Gain | 130 dB into 600 Ω - ensures <1 ppm gain error in precision instrumentation amplifier front-ends. |
| Total Harmonic Distortion + Noise | 0.00008% at 1 kHz - meets high-fidelity audio and test equipment linearity requirements. |
Pinout & Package
OPA132UAE4 is housed in an 8-pin SOIC (SO-8) package measuring 4.90 mm × 3.91 mm, with standard JEDEC MS-012AC footprint and gull-wing leads. Pin 1 is offset trim (input offset adjust), pin 2 is inverting input, pin 3 is noninverting input, pin 4 is negative supply (V–), pin 5 is no-connect (NC), pin 6 is output, pin 7 is positive supply (V+), and pin 8 is second offset trim terminal.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 8 | Offset Trim | Connect external 10 kΩ potentiometer between pins 1 and 8, wiper to V–, to null input offset voltage (typical trim range ±4 mV). |
| 2 | Inverting Input | Differential input node for feedback networks; high-impedance JFET input (10¹³ Ω || 2 pF). |
| 3 | Noninverting Input | Differential input node for reference or signal injection; identical impedance and noise performance as pin 2. |
| 4 | V– | Negative power supply connection; supports rail-to-rail input common-mode down to (V–) + 0.3 V. |
| 5 | NC | No internal connection; must be left floating or tied to ground (no electrical function). |
| 6 | Output | Class-AB output stage capable of ±40 mA short-circuit current and ±2.5 V swing into 600 Ω. |
| 7 | V+ | Positive power supply connection; supports rail-to-rail input common-mode up to (V+) – 0.3 V. |
Key Features
| Feature | Design Value |
|---|---|
| FET input stage with cascode topology | Maintains ≤50 pA input bias current across full ±13 V common-mode range - eliminates input stage saturation errors in high-Z transducer buffers. |
| Unity-gain stability | Operates without external compensation in voltage-follower, integrator, or active filter configurations - reduces BOM count and layout complexity. |
| No phase reversal on common-mode overvoltage | Prevents catastrophic control loop failure in voltage-follower applications when input exceeds supply rails - unlike many legacy JFET op-amps. |
| Laser-trimmed input offset voltage | ≤500 µV max (25°C) - enables DC-coupled precision gain stages without external nulling in most applications. |
| High capacitive load drive capability | Stable with ≥100 pF load capacitance - simplifies PCB routing and sensor cable interfacing without isolation resistors. |
Applications
| SAR ADC Driver | Voltage Reference Buffer |
|---|---|
Use Scenario: Driving the switched-capacitor input of a 16-bit SAR ADC with 1 MSPS sampling rate. IC Role / Device Role / Timing Role: Precision buffer isolating reference voltage from dynamic ADC input current spikes. Use Value: Low 8 nV/√Hz noise and ±50 pA bias current prevent code-dependent errors and maintain effective resolution >15.5 ENOB. |
Use Scenario: Stabilizing and distributing a 2.5 V bandgap reference to multiple precision DACs. IC Role / Device Role / Timing Role: Low-drift, low-noise unity-gain follower maintaining reference accuracy under varying load conditions. Use Value: 130 dB open-loop gain and 0.00008% THD+noise ensure reference integrity remains within ±1 µV across temperature and load. |
| Trans-impedance Amplifier | Photodiode Amplifier |
Use Scenario: Converting photocurrent from a 100 pA–10 µA photodiode into measurable voltage. IC Role / Device Role / Timing Role: High-gain, low-noise trans-impedance stage with guarded input and low input capacitance. Use Value: ≤50 pA input bias current minimizes dark-current-induced offset; 8 MHz bandwidth supports >100 kHz optical modulation detection. |
Use Scenario: Amplifying weak signals from a reverse-biased silicon photodiode in spectrophotometry. IC Role / Device Role / Timing Role: Low-noise, high-common-mode-rejection front-end amplifier operating in photovoltaic mode. Use Value: 100 dB CMRR and 8 nV/√Hz noise preserve signal-to-noise ratio for sub-nA photocurrent measurements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed, low-input-bias-current operational amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| OPA140AIDBVR | Lower input bias current (1 pA typ), higher GBP (11 MHz), but narrower supply range (±4.5 V to ±18 V); no offset trim pins. | Better for femtoampere-level current measurement; unsuitable where ±2.5 V operation or user-adjustable offset is required. | Select OPA140AIDBVR when ultimate input bias current and bandwidth outweigh need for low-voltage operation or offset trimming. |
| ADA4625-1ACPZ-R7 | Higher slew rate (34 V/µs), lower noise (4.2 nV/√Hz), but higher quiescent current (3.4 mA vs 4.8 mA) and no offset trim. | Preferred for high-speed pulse amplification and low-noise audio; not pin-compatible and requires different bypassing strategy. | Choose ADA4625-1ACPZ-R7 when 34 V/µs slew rate and 4.2 nV/√Hz noise are mandatory, and SOIC-8 pinout compatibility is secondary. |
Compared with OPA132UAE4, OPA140AIDBVR offers superior input bias current and bandwidth but sacrifices ±2.5 V operation and user-adjustable offset; ADA4625-1ACPZ-R7 delivers lower noise and faster slew rate but increases power and removes offset trim functionality - making OPA132UAE4 the optimal choice for cost-sensitive, low-voltage, or offset-calibrated high-impedance sensor interfaces.
Availability
OPA132UAE4 is available at Aetrix Electronics and suitable for SAR ADC driver circuits, photodiode amplifiers, voltage reference buffers, and trans-impedance amplifier designs requiring stable component supply with guaranteed long-term manufacturability.
Supply support for OPA132UAE4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company delivering analog and embedded processing solutions, with leadership in precision op-amps, data converters, and power management ICs since 1930.
The OPA132UAE4 belongs to TI's OPAx132 family of high-speed FET-input op-amps, engineered specifically for precision signal conditioning in high-source-impedance applications such as sensor interfaces, medical instrumentation, and test equipment.
FAQ
What is the maximum supply voltage for OPA132UAE4?
The absolute maximum supply voltage for OPA132UAE4 is ±18 V (36 V total), with recommended operation from ±2.5 V to ±15 V. Exceeding ±18 V risks permanent damage per TI's Absolute Maximum Ratings. The device maintains specified performance across the full ±2.5 V to ±18 V range, including low-voltage battery-powered systems and industrial ±15 V rails. Always use 10 nF ceramic bypass capacitors at V+ and V– pins to ensure stability under transient load conditions.
Does OPA132UAE4 require external compensation for unity-gain stability?
No, OPA132UAE4 is internally compensated for unity-gain stability and operates reliably in voltage-follower, active filter, and integrator configurations without external components. Its 8 MHz gain-bandwidth and ±20 V/µs slew rate are fully characterized under unity-gain conditions. Stability is maintained with capacitive loads up to 100 pF; for larger loads, a small series resistor (10–50 Ω) at the output may be added to isolate capacitance without affecting DC accuracy.
Can OPA132UAE4 be used with a single supply?
Yes, OPA132UAE4 supports single-supply operation with V– grounded and V+ ranging from +5 V to +36 V. Input common-mode range extends from (V–) + 0.3 V to (V+) – 1.2 V at RL = 10 kΩ, enabling rail-to-rail input capability near ground. Output swings to within 0.3 V of ground and 1.2 V below V+, so proper level-shifting or biasing is required for true rail-to-rail output. Use dual supplies (±Vs) for symmetrical AC-coupled applications or when full bipolar signal swing is needed.
What is the purpose of pins 1 and 8 on OPA132UAE4?
Pins 1 and 8 on OPA132UAE4 are dedicated offset voltage trim terminals. They allow adjustment of input offset voltage using an external 10 kΩ potentiometer connected between pins 1 and 8, with the wiper tied to V–. This feature enables fine nulling of residual offset (typical trim range ±4 mV) in DC-critical applications like precision instrumentation amplifiers. Offset trim is optional - the device is laser-trimmed to ≤500 µV max, and excessive adjustment can degrade offset drift performance.
How does OPA132UAE4 handle input common-mode overvoltage?
OPA132UAE4 incorporates cascode input circuitry that prevents phase reversal when input common-mode voltage exceeds the supply rails - a failure mode common in basic JFET-input op-amps. This design ensures predictable output behavior even in voltage-follower configurations where the input may momentarily exceed V+ or fall below V–. Common-mode rejection remains ≥96 dB across –12.5 V to +12.5 V, supporting robust operation in noisy industrial environments without latch-up or output inversion.
OPA132UAE4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Amplifier Type:
- General Purpose
- Number of Circuits:
- 1
- Output Type:
- -
- Slew Rate:
- 20V/µs
- Gain Bandwidth Product:
- 8 MHz
- -3db Bandwidth:
- -
- Current - Input Bias:
- 5 pA
- Voltage - Input Offset:
- 500 µV
- Current - Supply:
- 4mA
- Current - Output / Channel:
- 40 mA
- Voltage - Supply Span (Min):
- 5 V
- Voltage - Supply Span (Max):
- 36 V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
OPA132UAE4 FAQ
1.How can I place an order for OPA132UAE4 through Aetrix?
Please submit a Request for Quotation (RFQ) for OPA132UAE4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for OPA132UAE4 reliable?
The price and inventory of OPA132UAE4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for OPA132UAE4 is usually 5 days.
3.What payment methods are accepted for OPA132UAE4?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for OPA132UAE4 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for OPA132UAE4?
OPA132UAE4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your OPA132UAE4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for OPA132UAE4?
For technical support, including OPA132UAE4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your OPA132UAE4 requirements.
6.How does Aetrix verify that OPA132UAE4 is sourced from the original manufacturer or authorized distributors?
All OPA132UAE4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that OPA132UAE4 meets industry standards.
7.What is the process for return or replacement of OPA132UAE4?
All OPA132UAE4 units undergo pre-shipment inspection (PSI). If there is an issue with OPA132UAE4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The OPA132UAE4 part is unused and in its original packaging.
Return procedure for OPA132UAE4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
OPA132UAE4 Tags

-
LM358DT
STMicroelectronics

-
LM358DR
Texas Instruments

-
LM2904DR
Texas Instruments

-
LM358ADR
Texas Instruments
-
LM2904DGKR
Texas Instruments
-
LM324DR
Texas Instruments

-
MCP6006T-E/OT
Microchip Technology

-
MCP6006UT-E/OT
Microchip Technology

-
LM324PWR
Texas Instruments

-
LM2902PWR
Texas Instruments
-
LM2902DR
Texas Instruments

-
LM358P
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
