Texas Instruments OPA2625IDGSR
- Part No.:
- OPA2625IDGSR
- Manufacturer:
- Texas Instruments
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
OPA2625IDGSR.pdf
- Description:
- IC OPAMP VFB 2 CIRCUIT 10VSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
OPA2625IDGSR from Texas Instruments is a dual, high-precision, power-scalable operational amplifier optimized as a SAR ADC driver for 16-bit and 18-bit systems. It delivers 120 MHz gain-bandwidth, 115 V/µs slew rate, and 2.5 nV/√Hz input voltage noise at 10 kHz, enabling 16-bit settling in 280 ns when driving precision converters like the ADS8860.
For engineers reviewing the OPA2625IDGSR datasheet, OPA2625IDGSR pinout, OPA2625IDGSR application, or OPA2625IDGSR equivalent, key selection criteria include dual-channel independent mode control, low THD+N (–122 dBc HD2 / –140 dBc HD3 at 100 kHz), rail-to-rail output swing, and ultrafast 170 ns transition from low-power to high-drive mode.
Technical Context
The OPA2625IDGSR integrates two fully independent amplifiers, each with dedicated MODE A and MODE B pins enabling per-channel selection between high-drive (120 MHz GBW, 2 mA IQ) and low-power (1 MHz GBW, 270 µA IQ) modes. Its architecture supports fast transient response with 170 ns mode-switching latency and maintains <50 µV settling accuracy within 180 ns during LP→HD transitions.
It features rail-to-rail output, input common-mode range extending to the negative rail, and robust AC/DC precision: ±100 µV max offset voltage, ±3 µV/°C drift, and >110 dB open-loop gain at 10 kΩ load - all specified across –40°C to +125°C for industrial and automotive data acquisition.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Gain-bandwidth product (HD mode) | 120 MHz - enables stable G ≥ 2 configurations up to ~60 MHz signal bandwidth for SAR ADC front-ends. |
| Slew rate (HD mode) | 115 V/µs - supports full-scale step response without slewing distortion for 4-V output steps in <35 ns. |
| THD+N (100 kHz) | –122 dBc (HD2), –140 dBc (HD3) - preserves ENOB >14.9 in high-resolution ADC sampling at 1 MSPS. |
| Input voltage noise density | 2.5 nV/√Hz @ 10 kHz - contributes <0.5 LSB noise to 16-bit, 2 VPP full-scale systems. |
| Settling time (16-bit) | 280 ns to 0.00153% - guarantees accurate sampling of 1-MSPS SAR ADCs with no cycle loss. |
| Mode transition time (LP→HD) | 170 ns - allows dynamic power scaling synchronized to ADC conversion windows without timing penalty. |
| Supply voltage range | 2.7 V to 5.5 V - supports single-supply operation with 3.3 V or 5 V rails in portable and industrial systems. |
Pinout & Package
OPA2625IDGSR is housed in a 10-pin VSSOP (DGS) package measuring 3.00 mm × 3.00 mm, optimized for space-constrained PCB layouts while maintaining thermal performance (RθJA = 171.7 °C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| OUT A | Output terminal for channel A | Drives ADC input A; rail-to-rail swing supports full dynamic range utilization. |
| +IN A | Noninverting input for channel A | Accepts differential or single-ended signals; includes negative rail support for ground-referenced sources. |
| –IN A | Inverting input for channel A | Enables precision gain-setting with external feedback network; matched to +IN A for CMRR >115 dB. |
| MODE A | Mode control for channel A | V– = high-drive; V+ = low-power; must not be floated - enables per-channel power optimization. |
| OUT B | Output terminal for channel B | Independent output for second ADC channel or reference buffer; electrically isolated from channel A. |
| +IN B | Noninverting input for channel B | Identical electrical specs to +IN A; supports dual-sensor or dual-channel acquisition. |
| –IN B | Inverting input for channel B | Matches –IN A in offset, bias current, and impedance for crosstalk < –127 dB at 1 MHz. |
| MODE B | Mode control for channel B | Independent of MODE A; allows asymmetric power states (e.g., A=HD, B=LP) for mixed-workload systems. |
| V+ | Positive supply voltage | Accepts 2.7–5.5 V; PSRR >100 dB ensures immunity to digital supply noise coupling into analog path. |
| V– | Negative supply voltage | Typically ground; supports true single-supply operation with input down to V– and rail-to-rail output. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent mode control | Separate MODE A/MODE B pins allow per-amplifier selection between high-drive (120 MHz) and low-power (1 MHz) modes - critical for burst-mode data acquisition. |
| 16-bit settling in 280 ns | Guaranteed 0.00153% settling for 4-V step ensures no missing codes in 1-MSPS 16-bit SAR ADCs like ADS8860 without added delay cycles. |
| Ultra-low distortion at 100 kHz | –122 dBc HD2 and –140 dBc HD3 enable >14.9 ENOB in wideband sensor signal chains without post-processing correction. |
| Rail-to-rail output with 20 mV swing | Delivers >99% of full-scale range at 10 kΩ load - maximizes ADC utilization and SNR in single-supply systems. |
| Input common-mode to negative rail | Supports direct connection of ground-referenced transducers (e.g., strain gauges, thermocouples) without level-shifting circuitry. |
Applications
| High-Speed Precision Data Acquisition | Dual-Channel Sensor Signal Conditioning |
|---|---|
Use Scenario: Simultaneous sampling of two 16-bit SAR ADCs in automated test equipment requiring <1 µs inter-channel skew and <0.002% linearity error. IC Role / Device Role / Timing Role: Dual-channel ADC driver with independent MODE control synchronizing drive strength to each ADC's conversion window. Use Value: Eliminates need for discrete op-amps and mode logic; 170 ns LP→HD transition ensures zero-cycle latency penalty during burst sampling. | Use Scenario: Isolated measurement of differential pressure and temperature in industrial PLC I/O modules using separate 18-bit SAR ADCs. IC Role / Device Role / Timing Role: Dual precision buffer with matched DC specs (±100 µV VOS, ±3 µV/°C drift) and <–127 dB crosstalk at 1 MHz. Use Value: Maintains channel independence and system-level accuracy without calibration overhead or guard traces. |
| Voltage Reference Buffering | Power-Sensitive Portable Instrumentation |
Use Scenario: Driving high-impedance inputs of multiple 16-bit ADCs from a single precision voltage reference (e.g., REF5025) in medical ECG front-ends. IC Role / Device Role / Timing Role: Low-noise, low-offset buffer with rail-to-rail output ensuring full reference voltage delivery under varying load conditions. Use Value: 2.5 nV/√Hz noise and ±100 µV offset prevent reference-induced gain/offset errors in multi-channel biopotential acquisition. | Use Scenario: Battery-powered handheld multimeter with dual 16-bit ADCs sampling voltage and current simultaneously. IC Role / Device Role / Timing Role: Power-scalable dual op-amp operating in low-power mode between measurements and switching to high-drive only during active sampling. Use Value: Reduces average quiescent current from 4 mA to <600 µA - extends battery life by >3× versus fixed high-performance amplifiers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel precision op-amp applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| OPA2189IDRCT | Zero-drift architecture; 5.7 nV/√Hz noise; no mode control; 2 MHz GBW; 0.02 µV/°C drift | Better DC stability over temperature but insufficient bandwidth for >200 kSPS SAR ADC drivers | Select for ultra-low drift metrology where speed <1 MHz suffices; not suitable for ADS8860-class ADCs. |
| ADA4898-2ARMZ | Fixed high-speed design; 1 GHz GBW; 210 V/µs slew; 1.1 nV/√Hz noise; no power-scaling | Higher bandwidth/noise performance but 12 mA IQ per channel - unsuitable for power-constrained systems | Select when maximum speed and lowest noise are mandatory and power budget allows >24 mA total IQ. |
Compared with OPA2189IDRCT and ADA4898-2ARMZ, the OPA2625IDGSR uniquely balances 120 MHz bandwidth, 2.5 nV/√Hz noise, and dynamic power scaling - making it the only dual op-amp capable of meeting both 16-bit settling and sub-mA average current requirements in portable high-resolution DAQ.
Availability
OPA2625IDGSR is available at Aetrix Electronics and suitable for high-speed precision data acquisition, dual-channel sensor conditioning, and power-sensitive portable instrumentation requiring stable component supply across extended temperature ranges (–40°C to +125°C).
Supply support for OPA2625IDGSR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in precision signal chain components.
The OPAx625 product line was designed specifically to solve the dual challenge of driving high-throughput, high-resolution SAR ADCs while minimizing system power - targeting applications from industrial PLCs to portable medical devices.
FAQ
What is the maximum recommended capacitive load for OPA2625IDGSR in high-drive mode?
The OPA2625IDGSR supports stable operation with up to 1.2 nF capacitive load in high-drive mode when using appropriate series isolation resistance (e.g., 10 Ω to 50 Ω). Figure 14 in the SBOS688A datasheet shows overshoot remains <5% with Riso = 25 Ω and CL = 1.2 nF, confirming robust drive capability for ADC input capacitance and PCB trace parasitics without external compensation.
Does OPA2625IDGSR support true single-supply operation with input signals referenced to ground?
Yes, the OPA2625IDGSR supports true single-supply operation: its input common-mode range extends to the negative rail (V–), and its output swings rail-to-rail. With V– = 0 V and V+ = 3.3 V or 5 V, it accepts ground-referenced sensor signals and delivers full-scale output - eliminating level-shifters in designs using ADS8860 or similar SAR ADCs.
How does the MODE pin function differ between OPA2625IDGSR and single-channel OPA625?
The OPA2625IDGSR has two independent MODE pins (MODE A and MODE B), allowing per-channel selection of high-drive or low-power mode. In contrast, the single-channel OPA625 uses one MODE pin. This dual-control architecture enables asymmetric power states - for example, channel A in high-drive during ADC sampling while channel B remains in low-power - a capability not available in the OPA625 or most competing dual op-amps.
What is the guaranteed settling time for 18-bit accuracy with OPA2625IDGSR?
The OPA2625IDGSR datasheet specifies 280 ns settling time to 0.00153% (16-bit) under standard test conditions. While 18-bit accuracy (0.00038%) is not explicitly guaranteed, typical performance reaches <400 ns at 5 V supply based on Figure 17's settling curves and 170 ns LP→HD transition latency - sufficient for 250 kSPS 18-bit SAR ADCs when combined with proper layout and decoupling.
Can OPA2625IDGSR drive an ADS8860 ADC directly without external filtering?
Yes, the OPA2625IDGSR is characterized and optimized for direct interface with the ADS8860: its 280 ns 16-bit settling, low THD+N (–122 dBc HD2 at 100 kHz), and 2.5 nV/√Hz noise meet ADS8860's full-scale dynamic performance requirements. TI's reference design TIPD175 confirms direct connection with no additional RC filter needed - though a small series resistor (<10 Ω) is recommended for stability with ADC input capacitance.
OPA2625IDGSR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Amplifier Type:
- Voltage Feedback
- Number of Circuits:
- 2
- Output Type:
- Rail-to-Rail
- Slew Rate:
- 115V/µs
- Gain Bandwidth Product:
- 120 MHz
- -3db Bandwidth:
- -
- Current - Input Bias:
- 2 µA
- Voltage - Input Offset:
- 15 µV
- Current - Supply:
- 2mA (x2 Channels)
- Current - Output / Channel:
- 120 mA
- Voltage - Supply Span (Min):
- 2.7 V
- Voltage - Supply Span (Max):
- 5.5 V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-VSSOP
OPA2625IDGSR FAQ
1.How can I place an order for OPA2625IDGSR through Aetrix?
Please submit a Request for Quotation (RFQ) for OPA2625IDGSR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for OPA2625IDGSR reliable?
The price and inventory of OPA2625IDGSR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for OPA2625IDGSR is usually 5 days.
3.What payment methods are accepted for OPA2625IDGSR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for OPA2625IDGSR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for OPA2625IDGSR?
OPA2625IDGSR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your OPA2625IDGSR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for OPA2625IDGSR?
For technical support, including OPA2625IDGSR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your OPA2625IDGSR requirements.
6.How does Aetrix verify that OPA2625IDGSR is sourced from the original manufacturer or authorized distributors?
All OPA2625IDGSR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that OPA2625IDGSR meets industry standards.
7.What is the process for return or replacement of OPA2625IDGSR?
All OPA2625IDGSR units undergo pre-shipment inspection (PSI). If there is an issue with OPA2625IDGSR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The OPA2625IDGSR part is unused and in its original packaging.
Return procedure for OPA2625IDGSR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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