Texas Instruments OPA2835IDGSR
- Part No.:
- OPA2835IDGSR
- Manufacturer:
- Texas Instruments
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
OPA2835IDGSR.pdf
- Description:
- IC OPAMP VFB 2 CIRCUIT 10VSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:3,168
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
OPA2835IDGSR from Texas Instruments is a dual ultra-low-power, rail-to-rail output, negative-rail input voltage-feedback operational amplifier in a 10-pin VSSOP package. It delivers 56 MHz bandwidth, 160 V/µs slew rate, and 250 µA/ch quiescent current at 5 V supply, enabling high-fidelity signal conditioning in battery-powered portable systems such as ultrasonic flow meters and SAR ADC drivers.
For engineers reviewing the OPA2835IDGSR datasheet, OPA2835IDGSR pinout, OPA2835IDGSR application, or OPA2835IDGSR equivalent, key selection criteria include its –40°C to +125°C operating range, 0.5 µA power-down mode, 9.3 nV/√Hz input voltage noise, and validated channel-to-channel crosstalk of –120 dB - all critical for low-power, high-density analog front-ends.
Technical Context
The OPA2835IDGSR implements a voltage-feedback (VFB) architecture with fully differential input stage referenced to the negative rail, supporting common-mode input down to –0.2 V (at 5 V supply). Its unity-gain-stable design achieves 56 MHz small-signal bandwidth and 31 MHz gain-bandwidth product while maintaining 0.1% settling in 55 ns for 2-V step inputs.
Each amplifier features independent power-down control (PD1/PD2 pins), enabling selective channel disablement without affecting the other channel. The device operates from 2.5 V to 5.5 V single supply or ±1.25 V to ±2.75 V dual supply, with rail-to-rail output swing and 40 mA output drive capability into 2 kΩ loads.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Bandwidth (AV = 1) | 56 MHz - supports high-speed signal acquisition up to ~31 MHz full-power bandwidth for 2-VPP outputs. |
| Slew Rate | 160 V/µs - enables clean reproduction of fast transients without slewing distortion in ADC driver applications. |
| Quiescent Current | 250 µA per channel - allows continuous operation in multi-channel, battery-powered systems for >1 year on coin-cell batteries. |
| Power-Down Current | 0.5 µA typical - reduces system standby power by >500× versus active mode, critical for duty-cycled sensors. |
| Input Voltage Noise | 9.3 nV/√Hz at 100 kHz - preserves SNR in precision audio and instrumentation signal chains with minimal added noise floor. |
| CMRR | 113 dB - rejects common-mode interference in noisy industrial environments, ensuring stable DC accuracy. |
| Operating Temperature | –40°C to +125°C - qualified for under-hood automotive, industrial motor control, and extended-range portable equipment. |
Pinout & Package
The OPA2835IDGSR is housed in a 10-pin VSSOP (DGS) package measuring 3.00 mm × 3.00 mm with 0.5-mm lead pitch. This thermally enhanced, surface-mount package supports automated assembly and provides improved thermal resistance (RθJA = 206°C/W) versus SOIC.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN1– | Inverting input, Channel 1 | Accepts differential input signals referenced to negative rail; supports –0.2 V to 3.9 V common-mode range at 5 V supply. |
| VIN1+ | Noninverting input, Channel 1 | Enables single-ended or differential configurations; high CMRR ensures rejection of supply noise. |
| VOUT1 | Output, Channel 1 | Rail-to-rail swing (within 20 mV of rails) drives 40 mA load; optimized for low-distortion driving of SAR ADC inputs. |
| VS– | Negative power supply | Reference node for input stage; allows true negative-rail input operation and simplifies single-supply biasing. |
| VS+ | Positive power supply | Supports 2.5–5.5 V operation; PSRR of 105 dB minimizes supply ripple coupling into output. |
| VIN2– | Inverting input, Channel 2 | Independent second channel with matched AC/DC performance; crosstalk < –120 dB prevents inter-channel interference. |
| VIN2+ | Noninverting input, Channel 2 | Enables dual-path signal processing (e.g., I/Q channels) without performance degradation from shared resources. |
| VOUT2 | Output, Channel 2 | Simultaneous dual-output capability eliminates need for discrete duplication in space-constrained designs. |
| PD1 | Power-down control, Channel 1 | Active-low logic input; drives channel into sub-µA state with 250 ns turn-on delay for rapid wake-up. |
| PD2 | Power-down control, Channel 2 | Independent enable/disable per channel enables dynamic power management in multi-sensor systems. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low quiescent current | 250 µA per channel enables always-on sensing in energy-harvesting and wearable devices without compromising speed. |
| 56-MHz unity-gain bandwidth | Delivers high-frequency fidelity for ultrasound imaging front-ends and wideband sensor interfaces up to 31 MHz. |
| Rail-to-rail output swing | Maximizes dynamic range across 2.5–5.5 V supplies, increasing effective resolution when driving 12–16-bit ADCs. |
| –120 dB channel crosstalk | Preserves signal integrity in dual-channel applications like stereo audio buffers or differential I/Q demodulation. |
| –40°C to +125°C operation | Validated performance over full industrial temperature range eliminates derating concerns in harsh environments. |
Applications
| Audio ADC Input Buffer | Low-Power SAR ADC Driver |
|---|---|
|
Use Scenario: Buffering microphone or line-level audio signals before digitization in portable voice recorders or IoT edge nodes. IC Role / Device Role / Timing Role: High-SNR, low-noise input buffer with rail-to-rail output swing to maximize ADC utilization. Use Value: 9.3 nV/√Hz input noise and –130 dBc THD preserve audio fidelity; 250 µA/ch current extends battery life beyond 12 months on CR2032. |
Use Scenario: Driving the input of 12–16-bit successive-approximation register (SAR) ADCs in portable medical monitors or handheld test equipment. IC Role / Device Role / Timing Role: Fast-settling, low-distortion driver ensuring accurate sampling within ADC acquisition window. Use Value: 55 ns 0.1% settling time and 160 V/µs slew rate meet timing requirements of 1 MSPS+ SAR converters without external compensation. |
| Ultrasonic Flow Meter Front-End | High-Density Portable Systems |
|
Use Scenario: Amplifying weak echo signals from piezoelectric transducers in battery-operated ultrasonic flow meters. IC Role / Device Role / Timing Role: Low-noise, high-bandwidth gain stage preceding analog signal processing and envelope detection. Use Value: 56 MHz bandwidth captures harmonics up to 3rd order; –120 dB crosstalk isolates transmit/receive paths in half-duplex configurations. |
Use Scenario: Integrating dual analog signal paths in compact handheld instruments where PCB area and thermal dissipation are constrained. IC Role / Device Role / Timing Role: Dual-channel op amp replacing two discrete amplifiers to reduce component count and layout complexity. Use Value: 3.00 mm × 3.00 mm VSSOP footprint saves >40% board area versus SOIC-8; 206°C/W RθJA enables reliable operation at 70°C ambient. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual ultra-low-power op amp applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| OPA2836IDGSR | Higher 205 MHz bandwidth and 560 V/µs slew rate; 1 mA/ch quiescent current - 4× higher power than OPA2835IDGSR. | Better suited for wideband RF IF stages or high-speed active filters where speed outweighs battery life. | Select OPA2836IDGSR only if >100 MHz bandwidth is required and power budget permits 1 mA/ch draw. |
| OPA2365AIDR | Lower 50 MHz bandwidth and 25 V/µs slew rate; 5 mA/ch quiescent current - 20× higher than OPA2835IDGSR. | Optimized for precision DC-coupled applications with lower noise floor (4.5 nV/√Hz) but insufficient speed for >1 MSPS ADCs. | Choose OPA2365AIDR when ultra-low offset (10 µV max) and low 1/f noise dominate over speed and power. |
Compared with OPA2835IDGSR, OPA2836IDGSR trades 4× higher power for >3.5× bandwidth, while OPA2365AIDR sacrifices speed and efficiency for superior DC precision - making OPA2835IDGSR the optimal balance for portable high-speed analog front-ends.
Availability
OPA2835IDGSR is available at Aetrix Electronics and suitable for ultrasonic flow meter front-ends, portable medical monitoring systems, and high-density IoT sensor nodes requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for OPA2835IDGSR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in high-performance op amps and precision signal chain solutions.
The OPAx835 family was designed specifically for battery-powered, high-speed analog signal conditioning - delivering industry-leading bandwidth-per-microwatt performance for portable instrumentation, medical devices, and industrial sensing.
FAQ
What is the maximum supply voltage for OPA2835IDGSR?
The OPA2835IDGSR supports a maximum supply voltage of 5.5 V across VS+ to VS–. Absolute maximum ratings specify that the total supply voltage must not exceed 5.5 V; operation above this risks permanent damage. At 5 V nominal supply, the device delivers its specified 56 MHz bandwidth and 160 V/µs slew rate while maintaining 250 µA/ch quiescent current - confirming robust performance at upper rail limits.
Does OPA2835IDGSR support true rail-to-rail input?
No, the OPA2835IDGSR does not support rail-to-rail input. It features negative-rail input capability - allowing the input common-mode range to extend 0.2 V below VS– - but the high-side input limit is 3.9 V at 5 V supply (i.e., 1.1 V below VS+). This architecture optimizes power efficiency and speed while retaining compatibility with single-supply systems using simple level-shifting networks for full-scale input capture.
How does the power-down mode function on OPA2835IDGSR?
The OPA2835IDGSR implements independent power-down control via PD1 and PD2 pins: pulling either pin low disables its respective amplifier channel, reducing quiescent current to 0.5 µA typical. Both channels remain fully functional when pins are high. Turn-on delay is 250 ns, and turn-off delay is 50 ns - enabling rapid cycling in burst-mode sensor systems. The pins must be actively driven; floating states are undefined and may cause erratic behavior.
What is the thermal resistance of OPA2835IDGSR in its VSSOP package?
The OPA2835IDGSR in the 10-pin VSSOP (DGS) package has a junction-to-ambient thermal resistance (RθJA) of 206°C/W under standard JEDEC JESD51-7 conditions. This value reflects its thermal performance on a 2-layer PCB with 1-in² copper pour. For high-temperature operation, designers should consider its junction-to-board resistance (RθJB) of 96.2°C/W and ensure adequate thermal vias beneath the exposed pad to maintain TJ ≤ 125°C at full load.
Can OPA2835IDGSR drive capacitive loads directly?
The OPA2835IDGSR is unity-gain stable but exhibits reduced phase margin with capacitive loads >100 pF. Driving larger capacitive loads (e.g., ADC input capacitance plus PCB trace) requires isolation via a series resistor (typically 10–50 Ω) placed between the amplifier output and the load. This maintains stability while preserving 55 ns 0.1% settling performance - verified in TI's typical application circuits for SAR ADC driving.
OPA2835IDGSR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Amplifier Type:
- Voltage Feedback
- Number of Circuits:
- 2
- Output Type:
- Differential, Rail-to-Rail
- Slew Rate:
- 160V/µs
- Gain Bandwidth Product:
- 31 MHz
- -3db Bandwidth:
- 3.1 MHz
- Current - Input Bias:
- 200 nA
- Voltage - Input Offset:
- 100 µV
- Current - Supply:
- 250µA (x2 Channels)
- Current - Output / Channel:
- 40 mA
- Voltage - Supply Span (Min):
- 2.5 V
- Voltage - Supply Span (Max):
- 5.5 V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-VSSOP
OPA2835IDGSR FAQ
1.How can I place an order for OPA2835IDGSR through Aetrix?
Please submit a Request for Quotation (RFQ) for OPA2835IDGSR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for OPA2835IDGSR reliable?
The price and inventory of OPA2835IDGSR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for OPA2835IDGSR is usually 5 days.
3.What payment methods are accepted for OPA2835IDGSR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for OPA2835IDGSR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for OPA2835IDGSR?
OPA2835IDGSR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your OPA2835IDGSR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for OPA2835IDGSR?
For technical support, including OPA2835IDGSR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your OPA2835IDGSR requirements.
6.How does Aetrix verify that OPA2835IDGSR is sourced from the original manufacturer or authorized distributors?
All OPA2835IDGSR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that OPA2835IDGSR meets industry standards.
7.What is the process for return or replacement of OPA2835IDGSR?
All OPA2835IDGSR units undergo pre-shipment inspection (PSI). If there is an issue with OPA2835IDGSR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The OPA2835IDGSR part is unused and in its original packaging.
Return procedure for OPA2835IDGSR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
OPA2835IDGSR Tags

-
LM358DT
STMicroelectronics

-
LM358DR
Texas Instruments

-
LM2904DR
Texas Instruments

-
LM358ADR
Texas Instruments
-
LM2904DGKR
Texas Instruments
-
LM324DR
Texas Instruments

-
MCP6006T-E/OT
Microchip Technology

-
MCP6006UT-E/OT
Microchip Technology

-
LM324PWR
Texas Instruments

-
LM2902PWR
Texas Instruments
-
LM2902DR
Texas Instruments

-
LM358P
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
