Texas Instruments OPA3681U/2K5
- Part No.:
- OPA3681U/2K5
- Manufacturer:
- Texas Instruments
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
OPA3681U/2K5.pdf
- Description:
- IC OPAMP CFA 3 CIRCUIT 16SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
OPA3681U/2K5 from Texas Instruments is a triple-channel, current-feedback operational amplifier optimized for high-speed video, ADC buffering, and RGB line driving. It delivers 225MHz bandwidth at G = +2 (±5V), 2100V/µs slew rate, ±4.0V output swing, 150mA output current per channel, and 6mA/ch quiescent supply current - enabling single-supply +5V operation in portable instrumentation and broadband imaging systems.
For engineers reviewing the OPA3681U/2K5 datasheet, OPA3681U/2K5 pinout, OPA3681U/2K5 application, or OPA3681U/2K5 equivalent, key selection criteria include guaranteed 190MHz small-signal bandwidth at +85°C, disable control with 25ns enable time, differential-to-single-ended capability, and SO-16 package compatibility with industrial temperature range (–40°C to +85°C).
Technical Context
The OPA3681U/2K5 implements a triple-channel current-feedback architecture with independent disable pins per channel, enabling precise power gating in MUXed video paths. Its transimpedance gain of 100kΩ (min) and low inverting input resistance (44Ω typ) define its current-mode signal path, while the improved high-frequency pinout minimizes parasitic capacitance at RF nodes.
Operation supports both dual-supply (±5V) and single-supply (+5V) configurations, with rail-to-rail input common-mode range (±3.5V min) and output swing limited by 1V headroom. The output stage delivers >135mA sourcing/sinking while maintaining <0.01° differential phase error in NTSC video applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Small-Signal Bandwidth (G = +2) | 225MHz @ +25°C (±5V); 110MHz min over –40°C to +85°C - ensures stable 1080p60 video amplification across industrial temp range |
| Slew Rate | 2100V/µs @ ±5V (4V step); 570V/µs min @ +85°C - enables clean 2Vp-p transient response in ADC driver applications |
| Output Current (per channel) | +190mA sourcing / –150mA sinking @ ±5V; +60mA min sinking @ +85°C - drives 75Ω video loads and 100Ω ADC inputs without clipping |
| Supply Current (3 ch) | 18mA max @ ±5V; 16.5mA max @ +85°C - enables low-power portable instrumentation with thermal derating margin |
| Disable Current (per channel) | 300µA max @ ±5V; enables >98% power reduction during video MUX idle states |
| Differential Phase Error | 0.01° @ NTSC, RL = 150Ω - meets broadcast-grade video timing fidelity requirements |
| Input Voltage Noise | 2.2nV/√Hz @ f > 1MHz - preserves SNR in high-gain, wideband signal chains |
Pinout & Package
OPA3681U/2K5 is housed in a 16-pin SOIC (SO-16) surface-mount package with θJA = 100°C/W, rated for –40°C to +85°C operation. Pin assignments are validated per TI SBOS095A datasheet Figure 1 and Package Drawing 265.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (–IN A) | Inverting input, Channel A | Current-summing node for Channel A; requires matched 499Ω feedback resistor for G = +2 |
| 2 (+IN A) | Non-inverting input, Channel A | High-impedance input (100kΩ || 2pF); used for DC biasing in single-supply video buffers |
| 3 (DIS B) | Disable control, Channel B | Active-low logic input; pulls output to high-Z when ≤1.5V; enables video MUX switching |
| 4 (–IN B) | Inverting input, Channel B | Independent current-input node for Channel B; isolated from other channels |
| 5 (+IN B) | Non-inverting input, Channel B | DC-bias reference point for Channel B; tied to VS/2 in single-supply RGB drivers |
| 6 (DIS C) | Disable control, Channel C | Per-channel shutdown control; supports independent power gating of three signal paths |
| 7 (–IN C) | Inverting input, Channel C | Third current-input node; identical electrical characteristics to Channels A/B |
| 8 (+IN C) | Non-inverting input, Channel C | Third high-Z input; used for VCM reference in triple ADC buffer topologies |
| 9 (DIS A) | Disable control, Channel A | First channel disable; open or high = normal operation; low = 300µA quiescent mode |
| 10 (+VS) | Positive supply | Accepts +5V or ±6V max; requires 0.1µF decoupling to –VS per TI layout guidelines |
| 11 (OUT A) | Output, Channel A | Capable of ±4.0V swing into no load; 3.9V min into 100Ω @ +25°C |
| 12 (–VS) | Negative supply | Required for bipolar operation; tied to ground in single-supply +5V mode |
| 13 (OUT B) | Output, Channel B | Identical drive capability to OUT A; supports simultaneous RGB component buffering |
| 14 (+VS) | Positive supply (duplicate) | Second +VS connection for low-inductance power routing; must be decoupled |
| 15 (OUT C) | Output, Channel C | Third independent output; enables triple-channel digitizer front-end designs |
| 16 (–VS) | Negative supply (duplicate) | Second –VS connection; improves PSRR and reduces ground bounce in multi-channel use |
Key Features
| Feature | Design Value |
|---|---|
| Triple current-feedback architecture | Enables simultaneous high-bandwidth processing of RGB or three ADC channels without inter-channel crosstalk degradation |
| Per-channel disable control | Reduces system power by >98% per idle channel; supports make-before-break switching for glitch-free video MUX transitions |
| Single-supply +5V operation | Delivers 3Vp-p output swing with >150MHz full-power bandwidth - eliminates need for split supplies in portable instruments |
| Improved high-frequency pinout | Minimizes parasitic capacitance at RF nodes, preserving >225MHz bandwidth and reducing peaking at G = +1 |
| Low distortion at video frequencies | –75dBc 2nd harmonic @ 5MHz, RL = 100Ω - meets NTSC/PAL composite video dG/dP specifications |
| Guaranteed performance over temperature | 110MHz min bandwidth and 570V/µs min slew rate specified from –40°C to +85°C - supports industrial embedded deployment |
Applications
| RGB Amplifiers | ADC Buffers |
|---|---|
Use Scenario: Driving analog RGB signals from graphics processors to display panels over 75Ω coaxial cables. IC Role / Device Role / Timing Role: Triple-channel voltage buffer with independent disable control per color channel for dynamic power management. Use Value: Maintains <0.01° differential phase and 0.005% differential gain error at 14.3MHz (NTSC), ensuring broadcast-grade color fidelity. | Use Scenario: Conditioning analog inputs for high-speed CMOS pipelined ADCs such as ADS831 (8-bit, 80Msps). IC Role / Device Role / Timing Role: Single-supply +5V driver delivering 3Vp-p output swing with >150MHz full-power bandwidth into 100Ω loads. Use Value: Preserves SFDR by contributing <–75dBc 2nd harmonic distortion - below ADC quantization noise floor. |
| High-Speed Imaging Channels | Cable Drivers |
Use Scenario: Signal conditioning in medical ultrasound or industrial X-ray detector front-ends requiring sub-10ns settling. IC Role / Device Role / Timing Role: Low-glitch amplifier with 12ns 0.02% settling time (2V step) and ±50mV turn-on glitch. Use Value: Enables accurate sampling of fast transient pulses without aperture uncertainty-induced distortion. | Use Scenario: Driving long 75Ω or 100Ω coaxial cables in test equipment and broadcast infrastructure. IC Role / Device Role / Timing Role: High-output-current buffer (150mA) with 0.03Ω closed-loop output impedance at 100kHz. Use Value: Compensates for cable loss up to 100m at 100MHz while maintaining flat group delay and minimal overshoot. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar triple-channel high-speed op amp applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| OPA3681E/2K5 | SSOP-16 package (θJA = 100°C/W), same electrical specs, but 0.64mm pitch vs SO-16's 1.27mm - requires finer PCB trace routing | Preferred for space-constrained portable instruments where board area is critical | Select OPA3681E/2K5 only if SSOP-16 footprint and reflow profile are validated; SO-16 offers easier assembly and thermal margin |
| OPA2681U | Dual-channel version (2 channels), identical per-channel specs, 14-pin SOIC - lacks third channel and one DIS pin | Suitable for dual-sensor imaging or stereo ADC buffering where third channel is unnecessary | Choose OPA2681U to reduce BOM count and cost when only two high-speed channels are required |
Compared with OPA3681E/2K5 and OPA2681U, the OPA3681U/2K5 provides identical triple-channel performance in the more manufacturable SO-16 package, making it optimal for industrial video systems requiring long-term supply stability and simplified assembly.
Availability
OPA3681U/2K5 is available at Aetrix Electronics and suitable for RGB amplifiers, ADC buffers, and high-speed imaging channels requiring stable component supply across industrial temperature ranges and long production lifecycles.
Supply support for OPA3681U/2K5 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in high-speed op amp design and precision signal chain solutions.
The OPA3681U/2K5 belongs to TI's OPAx681 family of current-feedback op amps, engineered specifically for wideband video, communications, and data acquisition systems demanding GHz-class small-signal bandwidth and sub-10ns settling performance.
FAQ
What is the maximum operating voltage for OPA3681U/2K5?
The OPA3681U/2K5 supports a maximum operating voltage range of ±6V (dual supply) or +12V (single supply), as specified in the Absolute Maximum Ratings table. Operation beyond these limits risks permanent damage. For reliable long-term performance, TI recommends staying within the specified ±5V or +5V operating conditions outlined in the Electrical Characteristics tables.
Does OPA3681U/2K5 support true rail-to-rail input and output?
No, the OPA3681U/2K5 is not a rail-to-rail device. Its common-mode input range is specified as ±3.5V minimum (with ±5V supplies), and output swing is ±4.0V minimum into no load. In single-supply +5V operation, the least positive output voltage is 1.0V (min), and most positive is 4.0V (min). These headroom requirements must be accounted for in biasing networks for video or ADC applications.
How does the disable function work on OPA3681U/2K5?
The OPA3681U/2K5 features three independent active-low disable pins (DIS A, DIS B, DIS C). When pulled ≤1.5V, each channel enters a high-impedance output state with supply current reduced to ≤300µA/ch. Leaving the pin open or holding it ≥3.3V enables normal operation. The disable timing is characterized at 25ns enable time and 100ns disable time, with ±50mV turn-on glitch typical.
Can OPA3681U/2K5 be used with single-ended inputs in a differential-to-single-ended configuration?
Yes - the OPA3681U/2K5 is explicitly characterized for differential-to-single-ended conversion. Its current-feedback architecture and balanced input structure allow implementation of such configurations using external resistors, as shown in TI's application diagrams (e.g., Figure 1 in SBOS095A). Performance metrics like harmonic distortion and bandwidth remain consistent with the datasheet's G = +2 test conditions.
What thermal considerations apply to OPA3681U/2K5 in SO-16 package?
The OPA3681U/2K5 in SO-16 has a thermal resistance θJA of 100°C/W. At maximum quiescent current (19.8mA @ ±5V) and worst-case ambient (+85°C), junction temperature rise is ~2°C - well below the 175°C absolute maximum. However, under heavy output loading (e.g., 150mA into 50Ω), power dissipation increases significantly; proper PCB copper area and airflow must be verified per TI's thermal design guidelines.
OPA3681U/2K5 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- SpeedPlus™
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Bulk
- Product Status:
- Active
- Amplifier Type:
- Current Feedback
- Number of Circuits:
- 3
- Output Type:
- -
- Slew Rate:
- 2100V/µs
- Gain Bandwidth Product:
- -
- -3db Bandwidth:
- 280 MHz
- Current - Input Bias:
- 30 µA
- Voltage - Input Offset:
- 1.3 mV
- Current - Supply:
- 18mA
- Current - Output / Channel:
- 190 mA
- Voltage - Supply Span (Min):
- 5 V
- Voltage - Supply Span (Max):
- 12 V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
OPA3681U/2K5 FAQ
1.How can I place an order for OPA3681U/2K5 through Aetrix?
Please submit a Request for Quotation (RFQ) for OPA3681U/2K5 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for OPA3681U/2K5 reliable?
The price and inventory of OPA3681U/2K5 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for OPA3681U/2K5 is usually 5 days.
3.What payment methods are accepted for OPA3681U/2K5?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for OPA3681U/2K5 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for OPA3681U/2K5?
OPA3681U/2K5 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your OPA3681U/2K5 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for OPA3681U/2K5?
For technical support, including OPA3681U/2K5 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your OPA3681U/2K5 requirements.
6.How does Aetrix verify that OPA3681U/2K5 is sourced from the original manufacturer or authorized distributors?
All OPA3681U/2K5 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that OPA3681U/2K5 meets industry standards.
7.What is the process for return or replacement of OPA3681U/2K5?
All OPA3681U/2K5 units undergo pre-shipment inspection (PSI). If there is an issue with OPA3681U/2K5, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The OPA3681U/2K5 part is unused and in its original packaging.
Return procedure for OPA3681U/2K5:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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