Texas Instruments OPA4130UA/2K5
- Part No.:
- OPA4130UA/2K5
- Manufacturer:
- Texas Instruments
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
OPA4130UA/2K5.pdf
- Description:
- IC OPAMP JFET 4 CIRCUIT 14SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
OPA4130UA/2K5 from Texas Instruments is a quad, precision FET-input operational amplifier optimized for low-power, high-impedance signal conditioning in battery-powered and portable instrumentation. It delivers 1 MHz gain-bandwidth, ±1 mV max input offset voltage, 530 µA per amplifier quiescent current, and 90 dB min CMRR across –40°C to +85°C - enabling accurate sensor interfacing in data acquisition systems.
For engineers reviewing the OPA4130UA/2K5 datasheet, OPA4130UA/2K5 pinout, OPA4130UA/2K5 application, or OPA4130UA/2K5 equivalent, key selection considerations include its FET-input bias current (≤20 pA), unity-gain stability with 10 nF capacitive load drive, independent amplifier channels for low crosstalk, and SO-14 package compatibility with space-constrained PCB layouts.
Technical Context
The OPA4130UA/2K5 employs cascoded FET input stage architecture to maintain ultra-low input bias current (<20 pA) over its full common-mode range (±13 V), eliminating phase reversal under overvoltage conditions. Its fully independent quad topology ensures no interaction between amplifiers during overload or short-circuit events.
It achieves 120 dB minimum open-loop gain and 90 dB minimum CMRR via laser-trimmed input differential pair and matched internal resistor networks. The design supports rail-to-rail output swing within 1.5 V of supply rails at ±15 V, with stable operation up to 10 nF load capacitance without external compensation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Quiescent Current | 530 µA per amplifier - enables multi-channel precision amplification in sub-1 mA total system power budgets. |
| Input Offset Voltage | ±1 mV max - ensures ≤1 LSB error in 12-bit ADC front-ends with 2 V full-scale range. |
| Gain-Bandwidth Product | 1 MHz - supports stable unity-gain buffering of DC–100 kHz signals with <0.1% settling in 5.5 µs. |
| Input Bias Current | 20 pA max at 25°C - preserves signal integrity from >100 MΩ source impedances (e.g., pH electrodes, piezoelectric sensors). |
| Common-Mode Rejection | 90 dB min - rejects >30 kΩ unbalanced noise coupling in industrial 4–20 mA loop receivers. |
| Supply Voltage Range | ±2.25 V to ±18 V - operates from single 5 V logic rails (±2.5 V) up to ±15 V industrial supplies without re-biasing. |
| Capacitive Load Drive | 10 nF - interfaces directly with anti-aliasing filters or long cables without oscillation or peaking. |
Pinout & Package
OPA4130UA/2K5 is housed in a 14-pin SOIC (SO-14) surface-mount package per JEDEC MS-012 variation AA, with 1.27 mm pitch, 8.65 mm × 3.91 mm body, and 1.75 mm max height - compatible with standard reflow profiles (MSL Level-3, 260°C peak).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Out A | Amplifier A output - drives loads up to ±18 mA; stable with ≥10 nF capacitive load. |
| 2 | –In A | Inverting input of Amp A - high-impedance FET node (ZIN = 1013 Ω || 3 pF). |
| 3 | +In A | Non-inverting input of Amp A - identical impedance and bias current to Pin 2. |
| 4 | V– | Negative supply rail - shared by all four amplifiers; requires local 10 nF ceramic bypass. |
| 5 | +In C | Non-inverting input of Amp C - electrically isolated from other channels; no crosstalk. |
| 6 | –In C | Inverting input of Amp C - maintains 20 pA bias current and 90 dB CMRR independently. |
| 7 | Out C | Amplifier C output - fully independent; unaffected by overload on Amp A, B, or D. |
| 8 | Out D | Amplifier D output - same AC/DC specs as Out A; enables 4-channel simultaneous sampling. |
| 9 | –In D | Inverting input of Amp D - referenced to V– (Pin 4); no shared substrate path with other inputs. |
| 10 | +In D | Non-inverting input of Amp D - matches Pin 5 performance; supports differential input configurations. |
| 11 | V+ | Positive supply rail - shared by all amplifiers; must be bypassed near Pin 11 with 10 nF capacitor. |
| 12 | +In B | Non-inverting input of Amp B - isolated layout prevents thermal or supply coupling to Amp A/C/D. |
| 13 | –In B | Inverting input of Amp B - maintains 20 pA bias current across –40°C to +85°C operating range. |
| 14 | Out B | Amplifier B output - delivers full 1 MHz bandwidth and 2 V/µs slew rate without interaction. |
Key Features
| Feature | Design Value |
|---|---|
| No phase reversal on common-mode overvoltage | Prevents catastrophic control-loop failure in voltage-follower sensor buffers when input exceeds rails. |
| Laser-trimmed input offset | Eliminates need for external nulling circuitry in most applications; ±1 mV max simplifies 12-bit system calibration. |
| Fully independent quad architecture | Ensures channel separation >120 dB at 1 kHz - critical for simultaneous multi-sensor readout without crosstalk. |
| Unity-gain stable with 10 nF load | Enables direct connection to RC filters or long traces without stability-compensation resistors or feedback tweaks. |
| Wide supply range (±2.25 V to ±18 V) | Supports single-supply 5 V systems (±2.5 V) and dual-supply ±15 V industrial designs using identical OPA4130UA/2K5 footprint. |
Applications
| Strain Gauge Signal Conditioning | Portable ECG Front-End |
|---|---|
|
Use Scenario: Amplifying microvolt-level Wheatstone bridge outputs from load cells in handheld torque meters. IC Role / Device Role / Timing Role: Instrumentation-grade DC-coupled gain stage with ultra-high input impedance and low drift. Use Value: 20 pA input bias current prevents bridge imbalance errors; 1 mV offset ensures <0.05% full-scale error at 20 mV span. |
Use Scenario: Biopotential amplification in battery-powered wearable ECG monitors with dry electrodes. IC Role / Device Role / Timing Role: First-stage AC-coupled amplifier with high common-mode rejection for 50/60 Hz interference suppression. Use Value: 90 dB CMRR rejects mains noise without active guarding; 530 µA per amp extends battery life to >72 hours on two AA cells. |
| High-Impedance pH Electrode Interface | Multi-Channel Thermocouple Amplifier |
|
Use Scenario: Buffering glass electrode outputs (>1 GΩ source impedance) in handheld pH meters. IC Role / Device Role / Timing Role: Unity-gain voltage follower isolating electrode from downstream filtering and ADC input. Use Value: FET input preserves signal integrity; no phase reversal prevents output latch-up when electrode potential drifts beyond rails. |
Use Scenario: Cold-junction compensation and linearization of eight thermocouple types in industrial data loggers. IC Role / Device Role / Timing Role: Four parallel precision gain stages (two per dual-opamp IC) for simultaneous cold-junction reference and signal amplification. Use Value: Independent quad topology allows concurrent processing of K-type and J-type thermocouples without inter-channel thermal coupling or offset drift. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar precision FET-input op amp applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| OPA4140AIDR | Lower offset drift (0.1 µV/°C vs 2 µV/°C), higher CMRR (110 dB), but 1.8 mA per amp quiescent current. | Better for high-precision lab equipment; unsuitable for battery-powered devices requiring <1 mA total supply current. | Select OPA4140AIDR only when offset drift dominates error budget and power is secondary. |
| ADA4625-4ARUZ | Higher bandwidth (8 MHz), lower noise (7.2 nV/√Hz), but 3.4 mA per amp and no phase-reversal immunity. | Suitable for wideband sensor signal chains; not recommended for DC-coupled high-Z sources where input overvoltage may occur. | Choose ADA4625-4ARUZ when bandwidth and noise outweigh robustness requirements. |
Compared with OPA4130UA/2K5, OPA4140AIDR trades 3.4× higher supply current for 5× lower offset drift, while ADA4625-4ARUZ doubles bandwidth and halves voltage noise at the cost of losing phase-reversal immunity and tripling quiescent power - making OPA4130UA/2K5 optimal for low-power, high-Z, DC-critical applications.
Availability
OPA4130UA/2K5 is available at Aetrix Electronics and suitable for portable medical devices, industrial sensor nodes, and battery-powered test equipment requiring stable component supply with guaranteed long-term availability and RoHS-compliant green packaging.
Supply support for OPA4130UA/2K5 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in precision op amp design and manufacturing.
The OPA130 series - including OPA4130UA/2K5 - was engineered specifically for low-power, high-impedance signal conditioning in portable and battery-operated instrumentation, prioritizing dc accuracy, input robustness, and channel independence.
FAQ
What is the maximum capacitive load the OPA4130UA/2K5 can drive without instability?
The OPA4130UA/2K5 is specified for stable operation with up to 10 nF capacitive load at unity gain, as confirmed in the Electrical Characteristics table and Typical Characteristics curves. This eliminates the need for isolation resistors when driving anti-aliasing filters or long PCB traces. Exceeding 10 nF may cause peaking or ringing; for larger loads, external compensation or a buffer stage is required. Always verify stability under actual board parasitics using small-signal step response testing.
Does the OPA4130UA/2K5 have offset voltage trim pins?
No, the OPA4130UA/2K5 does not provide offset trim pins. Only the single-channel OPA130 (e.g., OPA130UA) includes dedicated offset adjust pins (1 and 5). The OPA4130UA/2K5 uses laser trimming during wafer fabrication to achieve ±1 mV max input offset voltage, eliminating user adjustment. External trimming is unnecessary and not supported by the SO-14 pinout.
What is the operating temperature range for the OPA4130UA/2K5?
The OPA4130UA/2K5 is specified for operation from –40°C to +85°C, as documented in the Package Option Addendum and Absolute Maximum Ratings table. This range covers industrial and extended commercial environments. While the device survives storage up to +125°C, electrical performance parameters such as offset voltage drift and CMRR are only guaranteed within the –40°C to +85°C operating band.
Is the OPA4130UA/2K5 pin-compatible with other quad op amps like the LM324?
No, the OPA4130UA/2K5 is not pin-compatible with the LM324 or other legacy quad op amps. Its SO-14 pinout follows Texas Instruments' proprietary mapping (e.g., V– on Pin 4, V+ on Pin 11), whereas LM324 places V+ on Pin 4 and V– on Pin 11. Swapping them will cause immediate power rail reversal and device damage. Always consult the OPA4130UA/2K5 pin diagram before PCB layout.
How does the OPA4130UA/2K5 prevent phase reversal during input overvoltage?
The OPA4130UA/2K5 uses an input cascode circuit that maintains stable biasing of the FET differential pair across the full common-mode range (±13 V), preventing the input stage from saturating and reversing output polarity - a known failure mode in basic FET-input op amps. This behavior is verified in the Applications Information section and enables safe use in voltage-follower configurations with high-impedance sources prone to rail excursions.
OPA4130UA/2K5 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Amplifier Type:
- J-FET
- Number of Circuits:
- 4
- Output Type:
- -
- Slew Rate:
- 2V/µs
- Gain Bandwidth Product:
- 1 MHz
- -3db Bandwidth:
- -
- Current - Input Bias:
- 5 pA
- Voltage - Input Offset:
- 200 µV
- Current - Supply:
- 530µA (x4 Channels)
- Current - Output / Channel:
- 18 mA
- Voltage - Supply Span (Min):
- 4.5 V
- Voltage - Supply Span (Max):
- 36 V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SOIC
OPA4130UA/2K5 FAQ
1.How can I place an order for OPA4130UA/2K5 through Aetrix?
Please submit a Request for Quotation (RFQ) for OPA4130UA/2K5 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for OPA4130UA/2K5 reliable?
The price and inventory of OPA4130UA/2K5 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for OPA4130UA/2K5 is usually 5 days.
3.What payment methods are accepted for OPA4130UA/2K5?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for OPA4130UA/2K5 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for OPA4130UA/2K5?
OPA4130UA/2K5 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your OPA4130UA/2K5 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for OPA4130UA/2K5?
For technical support, including OPA4130UA/2K5 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your OPA4130UA/2K5 requirements.
6.How does Aetrix verify that OPA4130UA/2K5 is sourced from the original manufacturer or authorized distributors?
All OPA4130UA/2K5 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that OPA4130UA/2K5 meets industry standards.
7.What is the process for return or replacement of OPA4130UA/2K5?
All OPA4130UA/2K5 units undergo pre-shipment inspection (PSI). If there is an issue with OPA4130UA/2K5, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The OPA4130UA/2K5 part is unused and in its original packaging.
Return procedure for OPA4130UA/2K5:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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