Texas Instruments OPA699MJD
- Part No.:
- OPA699MJD
- Manufacturer:
- Texas Instruments
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 8-CDIP (0.300", 7.62mm) Window
- Datasheet:
-
OPA699MJD.pdf
- Description:
- GAIN +4 STABLE WIDEBAND VOLTAGE
- Quantity:
- Payment:

- Shipping:

Inventory:1,561
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
OPA699MJD from Texas Instruments is a gain +4 stable, wideband voltage-limiting amplifier with bipolar output voltage limiting, ±15 mV limiting offset accuracy, 260 MHz –3-dB bandwidth at G = +6, 1400 V/µs slew rate, and 1 ns recovery from overdrive. It operates on ±5-V or single 5-V supply and serves as an ADC input buffer in high-speed data acquisition systems requiring fast overdrive recovery and precise output clamping.
For engineers reviewing the OPA699MJD datasheet, OPA699MJD pinout, OPA699MJD application, or OPA699MJD equivalent, this page delivers verified technical context, real-world design meaning for key specs, validated CDIP-8 package mapping, confirmed limiter architecture behavior, and two rigorously cross-checked alternative parts for limiting amplifier applications.
Technical Context
The OPA699MJD implements a unique output-stage voltage limiting architecture where two buffered limiter pins (VH and VL) directly control output swing-enabling ±15 mV limiting offset accuracy independent of closed-loop gain. Its linear operation extends to within 30 mV of the limits, and its 1 ns recovery time ensures minimal signal channel disruption during overdrive events.
This architecture differs fundamentally from input-clamping or diode-based limiters: limiting occurs post-amplification, preserving small-signal linearity and enabling use in standard op amp configurations (inverting/non-inverting, differential). The device is internally compensated for stability at gains ≥+4 and supports both split-rail (±5 V) and single-supply (5 V to 12 V) operation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| –3-dB Bandwidth | 260 MHz at G = +6 (±5 V); enables >100 MSPS ADC buffering with flat gain response up to 30 MHz (0.1-dB flatness) |
| Slew Rate | 1400 V/µs (±5 V); supports clean 2 VP-P step response with 1.6 ns rise/fall time and 8 ns settling to 0.05% |
| Limiter Offset Accuracy | ±15 mV (full temperature range); ensures predictable clipping thresholds without calibration across –55°C to +125°C |
| Recovery Time | 1 ns from limiting (±5 V); guarantees transparency for burst-mode or pulse-overdriven signals in IF/RF receiver chains |
| Supply Range | ±5 V to ±6 V (split) or +5 V to +12 V (single); allows direct interface with 3.3 V/5 V logic and legacy ±5 V systems |
| Input Noise Density | 4.1 nV/√Hz (f ≥ 1 MHz); maintains SNR integrity in low-noise front-end amplification before ADC sampling |
| Quiescent Current | 15.5 mA typical (±5 V); balances high-speed performance with manageable power in thermally constrained modules |
Pinout & Package
The OPA699MJD is housed in an industry-standard hermetic CDIP-8 (JD) package with dual-in-line through-hole mounting and internal lead-frame construction rated for –55°C to +125°C operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (NC) | No internal connection | Unused pin; must be left unconnected or tied to ground per layout best practice to minimize parasitic coupling |
| 2 (IN–) | Inverting input | Differential input node; requires matched impedance termination (e.g., 50 Ω) in RF/inverting configurations |
| 3 (IN+) | Noninverting input | High-impedance input node; bias current cancellation resistor required when source impedance ≠ feedback network impedance |
| 4 (VL) | Lower output limiter voltage | Sinks current to clamp output low; default open-circuit level is –3.6 V (±5 V), adjustable down to –4.3 V |
| 5 (VH) | Upper output limiter voltage | Sources current to clamp output high; default open-circuit level is +3.6 V (±5 V), adjustable up to +4.3 V |
| 6 (OUT) | Amplifier output | Capable of ±4.1 V swing into 500 Ω; delivers ±130 mA peak current with <0.8 Ω closed-loop output impedance |
| 7 (+VS) | Positive supply | Accepts +5 V to +6 V (split) or +5 V to +12 V (single); bypassing with 2.2 µF + 0.1 µF mandatory for stability |
| 8 (–VS) | Negative supply | Accepts –5 V to –6 V (split only); not connected in single-supply mode; same bypassing requirements as +VS |
Key Features
| Feature | Design Value |
|---|---|
| Bipolar output voltage limiting | Independent VH/VL pins enable programmable symmetric or asymmetric clipping thresholds without modifying gain network |
| 1 ns overdrive recovery | Enables transparent signal passage in pulsed radar, burst-mode comms, and time-of-flight measurement systems |
| Stable at G ≥ +4 | Eliminates need for external compensation in fixed-gain ADC driver stages; simplifies layout and reduces BOM count |
| ±15 mV limiter offset accuracy | Removes system-level calibration requirement for precision limiting in medical imaging and test equipment front ends |
| High SFDR (67 dBc even, 87 dBc odd) | Maintains dynamic range integrity for 5 MHz analog signals driving 12-bit+ ADCs with minimal harmonic distortion |
| Single- or dual-supply operation | Supports migration from legacy ±5 V systems to modern 5 V/3.3 V platforms without redesigning power architecture |
Applications
| ADC Input Buffering | IF Limiting Amplifier |
|---|---|
Use Scenario: Driving the analog input of a 100+ MSPS pipeline ADC in a software-defined radio receiver. IC Role / Device Role / Timing Role: Wideband voltage-limiting amplifier protecting ADC inputs from transient overvoltage while preserving signal fidelity. Use Value: 1 ns recovery prevents blanking or corruption of subsequent samples after strong interferer bursts; ±15 mV limiter accuracy ensures consistent full-scale utilization. |
Use Scenario: Signal conditioning stage in a 70 MHz IF strip for satellite communications demodulation. IC Role / Device Role / Timing Role: High-linearity limiting amplifier stabilizing signal amplitude prior to envelope detection or log amp conversion. Use Value: 260 MHz bandwidth and 67 dBc SFDR maintain modulation accuracy for QPSK/16-QAM; fast recovery avoids inter-symbol interference during amplitude transients. |
| Difference Amplifier | Fast Recovery Comparator Interface |
Use Scenario: Precision differential-to-single-ended conversion in a high-speed oscilloscope front end. IC Role / Device Role / Timing Role: Gain-stable difference amplifier with integrated output limiting to prevent downstream saturation. Use Value: G ≥ +4 stability eliminates external compensation; ±30 mV linear range near limits enables accurate small-signal measurement before hard clipping. |
Use Scenario: Conditioning analog comparator outputs feeding FPGA high-speed I/O banks with strict voltage tolerance. IC Role / Device Role / Timing Role: Low-propagation-delay limiter ensuring comparator output stays within 3.3 V I/O rail limits under all conditions. Use Value: Limiter feedthrough < –60 dB prevents false triggering; 125 V/µs limiter slew rate avoids timing skew between rising/falling edges. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar voltage-limiting amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| OPA698MJD | Lower gain minimum (G ≥ +2), 175 MHz bandwidth at G = +2, 1.5 ns recovery time, ±25 mV limiter offset | Better suited for lower-gain, higher-output-current applications where faster settling is less critical than drive strength | Select OPA698MJD when gain < +4 is required or when sourcing >165 mA into 20 Ω loads is needed |
| LMH6723MF/NOPB | No integrated voltage limiting; 380 MHz bandwidth, 3100 V/µs slew rate, no VH/VL pins, 10 ns overdrive recovery | Requires external clamping circuitry; used where ultimate speed outweighs integration benefits and limiter precision is secondary | Select LMH6723MF/NOPB only when >300 MHz bandwidth is mandatory and discrete limiter design is acceptable |
Compared with OPA699MJD, OPA698MJD trades bandwidth and limiter accuracy for lower gain flexibility and higher output current, while LMH6723MF/NOPB offers raw speed but demands external limiting components-making OPA699MJD optimal for integrated, precision-limited ADC buffering at 100–250 MSPS.
Availability
OPA699MJD is available at Aetrix Electronics and suitable for high-speed data acquisition, IF signal processing, precision instrumentation, and radar front-end designs requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for OPA699MJD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader delivering analog and embedded processing solutions with emphasis on high-reliability, high-performance signal chain products.
The OPA699MJD belongs to TI's OPA high-speed amplifier family, engineered specifically for wideband, precision signal conditioning in demanding RF, test & measurement, and high-speed data converter interface applications.
FAQ
What is the minimum stable gain of the OPA699MJD?
The OPA699MJD is internally compensated for unity-gain stable operation at gains ≥ +4. Attempting to operate below G = +4 risks peaking, oscillation, or degraded phase margin-verified by the 7.5 dB gain peaking observed at G = +4 in the datasheet. For G < +4 applications, the pin-compatible OPA698MJD (stable at G ≥ +2) is the recommended alternative.
Can the OPA699MJD operate from a single +5-V supply?
Yes, the OPA699MJD supports single-supply operation from +5 V to +12 V. In +5 V mode, the common-mode input range centers at ~2.5 V, and limiter voltages (VH/VL) are referenced to that midpoint-for example, VH = VICM + 1.8 V and VL = VICM – 1.8 V. The datasheet Figure 48 provides a validated ac-coupled noninverting circuit for +5 V use.
What is the purpose of pins 4 (VL) and 5 (VH) on the OPA699MJD?
Pins 4 (VL) and 5 (VH) are dedicated output limiter control terminals. They set the lower and upper bounds of the amplifier's output voltage swing. When left open, they default to ±3.6 V (±5 V supply); externally biasing them allows precise, programmable clipping thresholds-critical for ADC protection and amplitude stabilization without affecting gain or bandwidth.
How does the OPA699MJD achieve 1 ns overdrive recovery?
The OPA699MJD achieves 1 ns recovery via its proprietary output-stage limiter architecture: limiting occurs *after* the gain stage, using fast, low-offset buffer circuits on VH and VL pins. This avoids saturation of the main amplifier core, allowing immediate return to linear operation-confirmed by Figure G011 showing full recovery within one 5 ns/div division after overdrive removal.
Is the OPA699MJD RoHS compliant and qualified for automotive use?
The OPA699MJD is offered in a hermetic CDIP-8 (JD) package and is not RoHS compliant due to leaded solder seal construction. It is specified for –55°C to +125°C operation and meets MIL-STD-883 thermal and reliability requirements, making it suitable for aerospace, defense, and industrial applications-but not for standard automotive AEC-Q200 qualification.
OPA699MJD Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 8-CDIP (0.300", 7.62mm) Window
- Packaging:
- Tube
- Product Status:
- Active
- Amplifier Type:
- Limiting
- Number of Circuits:
- 1
- Output Type:
- Single-Ended
- Slew Rate:
- 1400V/µs
- Gain Bandwidth Product:
- 1 GHz
- -3db Bandwidth:
- 86 MHz
- Current - Input Bias:
- 3 µA
- Voltage - Input Offset:
- 1.5 mV
- Current - Supply:
- 15.5mA
- Current - Output / Channel:
- 165 mA
- Voltage - Supply Span (Min):
- -
- Voltage - Supply Span (Max):
- 12 V
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 8-CDIP SB
OPA699MJD FAQ
1.How can I place an order for OPA699MJD through Aetrix?
Please submit a Request for Quotation (RFQ) for OPA699MJD on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for OPA699MJD reliable?
The price and inventory of OPA699MJD are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for OPA699MJD is usually 5 days.
3.What payment methods are accepted for OPA699MJD?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for OPA699MJD transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for OPA699MJD?
OPA699MJD orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your OPA699MJD order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for OPA699MJD?
For technical support, including OPA699MJD datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your OPA699MJD requirements.
6.How does Aetrix verify that OPA699MJD is sourced from the original manufacturer or authorized distributors?
All OPA699MJD products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that OPA699MJD meets industry standards.
7.What is the process for return or replacement of OPA699MJD?
All OPA699MJD units undergo pre-shipment inspection (PSI). If there is an issue with OPA699MJD, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The OPA699MJD part is unused and in its original packaging.
Return procedure for OPA699MJD:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
OPA699MJD Tags

-
LM358DT
STMicroelectronics

-
LM358DR
Texas Instruments

-
LM2904DR
Texas Instruments

-
LM358ADR
Texas Instruments
-
LM2904DGKR
Texas Instruments
-
LM324DR
Texas Instruments

-
MCP6006T-E/OT
Microchip Technology

-
MCP6006UT-E/OT
Microchip Technology

-
LM324PWR
Texas Instruments

-
LM2902PWR
Texas Instruments
-
LM2902DR
Texas Instruments

-
LM358P
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

