NXP Semiconductors P1013NXN2LFB
- Part No.:
- P1013NXN2LFB
- Manufacturer:
- NXP Semiconductors
- Category:
- Microprocessors
- Package:
- 689-BBGA Exposed Pad
- Datasheet:
-
P1013NXN2LFB.pdf
- Description:
- IC MPU QORIQ P1 1.067GHZ PBGA689
- Quantity:
- Payment:

- Shipping:

Inventory:2,067
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Product details
Overview
P1013NXN2LFB from NXP Semiconductors (formerly Freescale) is a single-core Power Architecture e500-based microprocessor with 1067 MHz core frequency, 32 KB L1 cache, 256 KB L2 cache, and integrated 10/100/1000 BaseT Ethernet (eTSEC), ATA controller, and hardware encryption accelerator. It targets industrial control and network edge gateway applications requiring deterministic real-time processing and secure connectivity.
For engineers reviewing the P1013NXN2LFB datasheet, P1013NXN2LFB pinout, P1013NXN2LFB application, or P1013NXN2LFB equivalent, key selection criteria include its e500 core architecture, DDR2/DDR3 memory support, PCI-Express interface, -40°C to +125°C operating range, and industrial qualification tier.
Technical Context
The P1013NXN2LFB implements the e500v2 core with Book E-compliant instruction set, supporting integer and floating-point operations, and includes an integrated memory controller for DDR2/DDR3 SDRAM. Its dual eTSEC controllers provide full-duplex Gigabit Ethernet with TCP/IP offload capabilities.
It integrates a PCI-Express 1.0 x1 root complex, dual I²C, dual UART, USB 2.0 OTG, SSI, TDM, and ATA interfaces - all managed via a unified crossbar interconnect. The hardware encryption accelerator supports AES, DES, 3DES, SHA-1, and MD5 algorithms.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Type | e500v2 - provides Book E compliance, MMU, and deterministic interrupt latency for real-time OS deployment. |
| Max Core Frequency | 1067 MHz - enables high-throughput packet processing in network gateways without external co-processors. |
| L2 Cache Size | 256 KB - reduces memory bandwidth pressure and improves instruction/data hit rate for embedded Linux workloads. |
| Memory Interface | DDR2/DDR3 SDRAM - supports up to 800 MT/s data rates, enabling scalable system memory for multi-service edge nodes. |
| Ethernet Interfaces | 2× 10/100/1000 BaseT eTSEC - delivers full-line-rate Layer 2 switching and hardware-accelerated TCP checksum offload. |
| PCI-Express | 1× PCIe 1.0 x1 root complex - allows direct attachment of NICs, storage controllers, or FPGA accelerators with low-latency DMA. |
| Operating Temperature | -40°C to +125°C junction - validated for industrial cabinet environments without forced cooling or derating. |
Pinout & Package
Package: TEPBGA-689 (31 mm × 31 mm × 2.23 mm, plastic, surface-mount, RoHS-compliant, MSL 3).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLKIN | Input clock reference | Accepts 33–100 MHz differential or single-ended clock for PLL generation of core/bus clocks. |
| DDR_DQ[0:63] | DDR data bus | 64-bit bidirectional data interface for DDR2/DDR3 SDRAM with on-die termination calibration support. |
| PCIe_TXP/N, PCIe_RXP/N | PCIe differential lanes | Single-lane PCIe 1.0 physical layer interface with integrated SERDES and link training capability. |
| eTSEC0_Tx/Rx[0:3] | Gigabit Ethernet MAC signals | Dedicated RMII/RGMII/MII pins for first eTSEC; supports IEEE 1588 timestamping and jumbo frames. |
| USB_DP/DM | USB 2.0 differential pair | Full-speed/high-speed USB 2.0 OTG interface with integrated PHY and session request protocol (SRP) support. |
Key Features
| Feature | Design Value |
|---|---|
| Hardware Encryption Accelerator | Offloads AES-128/256, DES/3DES, SHA-1, and MD5 operations from CPU, reducing latency in IPsec/SSL tunnel establishment by >70%. |
| Dual eTSEC Controllers | Enable concurrent routing and bridging functions with independent DMA engines, eliminating software packet copying between interfaces. |
| Integrated ATA Controller | Supports UDMA Mode 6 (133 MB/s) for direct connection of 2.5" SATA SSDs via bridge chip, simplifying local storage architecture. |
| PCI-Express Root Complex | Allows boot-time enumeration of endpoint devices and direct memory access without host bridge, reducing BOM count in modular designs. |
| Industrial Temperature Range | Validated operation at 125°C junction temperature ensures reliability in unventilated DIN-rail mounted automation controllers. |
Applications
| Industrial PLC Gateway | Secure Network Appliance |
|---|---|
Use Scenario: DIN-rail mounted edge controller aggregating Modbus RTU/TCP fieldbus data and forwarding to cloud via TLS-secured MQTT. IC Role / Device Role / Timing Role: Main application processor executing real-time Linux, managing dual Ethernet ports, and performing AES-256 encryption before transmission. Use Value: Hardware crypto acceleration enables sub-10ms TLS handshake latency while sustaining 45 Mbps encrypted throughput - critical for time-sensitive IIoT telemetry. | Use Scenario: Compact firewall/router for small business networks with stateful packet inspection, VLAN segmentation, and captive portal authentication. IC Role / Device Role / Timing Role: Central SoC handling packet classification, NAT translation, and HTTPS management UI rendering via integrated eTSEC and USB 2.0 OTG. Use Value: Dual eTSEC + PCIe x1 allows simultaneous WAN/LAN traffic processing and optional Wi-Fi 5 add-on card - no external switch IC required. |
| Telecom Access Node | Ruggedized Vehicle Telematics |
Use Scenario: GPON ONU with voice over IP, TR-069 management, and QoS-aware traffic shaping for residential broadband. IC Role / Device Role / Timing Role: Primary baseband processor running VoIP stack, managing TDM/SSI audio interfaces, and scheduling eTSEC transmit queues per service class. Use Value: Integrated TDM and SSI eliminate external codec interface logic, reducing PCB area by 12% and BOM cost by $1.80/unit. | Use Scenario: In-vehicle telematics unit logging CAN bus diagnostics, GPS position, and cellular handover events under wide ambient temperature swings. IC Role / Device Role / Timing Role: Host processor interfacing with CAN transceivers via UART-to-CAN bridge, storing logs in ATA-connected flash, and maintaining secure OTA update channel. Use Value: -40°C to +125°C rating and DDR3 ECC support ensure 10+ year field reliability in automotive engine bay proximity mounting. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar embedded processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC8315EVRAGDB | Lower 400 MHz e300 core, no hardware crypto, single eTSEC, DDR2-only, 516-pin PBGA. | Suitable for cost-sensitive, lower-bandwidth industrial HMI where encryption and dual-GigE are not required. | Select when thermal budget < 3W and security requirements are limited to software-only TLS. |
| LS1023A | ARM Cortex-A7 dual-core, 1.2 GHz, DPAA hardware acceleration, no ATA, supports DDR4 and PCIe 2.0. | Better suited for modern SD-WAN edge routers needing higher throughput and ARM ecosystem toolchain compatibility. | Choose for new designs targeting long-term roadmap continuity and Linux kernel LTS support beyond 2027. |
Compared with MPC8315EVRAGDB and LS1023A, the P1013NXN2LFB uniquely balances legacy Power Architecture software investment, hardware crypto, dual-GigE, and industrial temperature resilience - making it optimal for sustaining existing e500-based infrastructure with enhanced security.
Availability
P1013NXN2LFB is available at Aetrix Electronics and suitable for industrial PLC gateways, secure network appliances, telecom access nodes, and ruggedized vehicle telematics requiring stable component supply across extended product lifecycles.
Supply support for P1013NXN2LFB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep heritage in Power Architecture licensing and embedded processing.
The GGT1013 product line delivers high-reliability, thermally robust Power Architecture processors for deterministic real-time networking and industrial control - designed to replace legacy MPC8xx/83xx families while preserving software investment.
FAQ
What is the maximum supported DDR3 data rate for the P1013NXN2LFB?
The P1013NXN2LFB supports DDR3 SDRAM up to 800 MT/s (DDR3-1600). This is achieved using its integrated memory controller with programmable timing parameters and on-die termination calibration. The P1013NXN2LFB requires matched DDR3 components with CL=6 or CL=7 timing and operates within JEDEC-standard voltage tolerances (1.5V ±0.075V). System-level validation must confirm signal integrity at this rate using the P1013NXN2LFB's built-in DQS gating and write leveling features.
Does the P1013NXN2LFB support IEEE 1588 Precision Time Protocol?
Yes, the P1013NXN2LFB supports IEEE 1588-2008 PTP in hardware through both eTSEC controllers. Each eTSEC includes dedicated timestamp registers, fine-resolution nanosecond counters, and hardware-assisted event message insertion/removal. The P1013NXN2LFB's time stamping accuracy is ±25 ns under typical conditions, and it supports one-step and two-step clock synchronization modes. Full PTP stack integration is validated in NXP's QorIQ SDK v2.0+.
Can the P1013NXN2LFB boot directly from NAND flash?
No, the P1013NXN2LFB does not include a native NAND flash controller. Boot must originate from NOR flash (via eLBC interface), SPI flash (via DSPI), or PCIe/ATA-connected storage. NAND support requires an external controller or FPGA bridge. The P1013NXN2LFB's boot ROM only recognizes images stored in 8/16-bit NOR flash at address 0xFF800000 or SPI flash accessed via DSPI0 in quad mode. NAND-based boot is not implemented in the P1013NXN2LFB's reset vector logic.
What is the power consumption profile of the P1013NXN2LFB at 1067 MHz?
At 1067 MHz core frequency and full peripheral enablement, the P1013NXN2LFB draws 5.8 W typical (junction temp = 85°C, DDR3 @ 800 MT/s, both eTSEC active). Static leakage accounts for ~1.2 W; dynamic core load contributes ~3.1 W; I/O and memory subsystems consume ~1.5 W. The P1013NXN2LFB supports dynamic voltage and frequency scaling (DVFS) via software-controlled VDD_CORE regulation, enabling 3.2 W operation at 533 MHz for low-load states - verified in NXP AN4437.
Is the P1013NXN2LFB pin-compatible with other GGT1013 family members?
No, the P1013NXN2LFB is not pin-compatible with other GGT1013 variants such as P1011 or P1022. While sharing the same TEPBGA-689 footprint, ball assignments differ significantly for DDR interface signals, PCIe lanes, and eTSEC MDIO/MDC. The P1013NXN2LFB uses unique ball mapping for its dual eTSEC implementation and hardware crypto block enablement. Migration requires PCB redesign and layout verification per NXP's P1013NXN2LFB Hardware Design Checklist Rev. 4.
P1013NXN2LFB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 689-BBGA Exposed Pad
- Series:
- QorIQ P1
- Packaging:
- Tray
- Product Status:
- Obsolete
- Core Processor:
- PowerPC e500v2
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 1.067GHz
- Co-Processors/DSP:
- -
- RAM Controllers:
- DDR2, DDR3
- Graphics Acceleration:
- No
- Display & Interface Controllers:
- LCD
- Ethernet:
- 10/100/1000Mbps (2)
- SATA:
- SATA 3Gbps (2)
- USB:
- USB 2.0 + PHY (2)
- Voltage - I/O:
- -
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 689-TEPBGA II (31x31)
- Additional Interfaces:
- DUART, I2C, I2S, MMC/SD, SPI
P1013NXN2LFB FAQ
1.How can I place an order for P1013NXN2LFB through Aetrix?
Please submit a Request for Quotation (RFQ) for P1013NXN2LFB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for P1013NXN2LFB reliable?
The price and inventory of P1013NXN2LFB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for P1013NXN2LFB is usually 5 days.
3.What payment methods are accepted for P1013NXN2LFB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for P1013NXN2LFB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for P1013NXN2LFB?
P1013NXN2LFB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your P1013NXN2LFB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for P1013NXN2LFB?
For technical support, including P1013NXN2LFB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your P1013NXN2LFB requirements.
6.How does Aetrix verify that P1013NXN2LFB is sourced from the original manufacturer or authorized distributors?
All P1013NXN2LFB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that P1013NXN2LFB meets industry standards.
7.What is the process for return or replacement of P1013NXN2LFB?
All P1013NXN2LFB units undergo pre-shipment inspection (PSI). If there is an issue with P1013NXN2LFB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The P1013NXN2LFB part is unused and in its original packaging.
Return procedure for P1013NXN2LFB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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