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NXP Semiconductors P60D144PA4/9A24AFJ
- Part No.:
- P60D144PA4/9A24AFJ
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- -
- Datasheet:
-
P60D144PA4/9A24AFJ.pdf
- Description:
- IC SMART CARD CTLR
- Quantity:
- Payment:
- Shipping:
Inventory:1,205
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Product details
Overview
P60D144PA4/9A24AFJ from NXP Semiconductors is a secure high-performance dual-interface smart card controller featuring 144 KB EEPROM, 384 KB ROM, and 8.125 KB RAM. It integrates SmartMX2 CPU, Fame2 RSA/ECC coprocessor, and symmetric block cipher (AES/Triple-DES) hardware acceleration. Designed for e-passports, ID cards, and contactless banking, it supports concurrent ISO/IEC 7816 (T=0/T=1) and ISO/IEC 14443A (106–848 kbit/s) operation across 1.62–5.5 V supply.
For engineers reviewing the P60D144PA4/9A24AFJ datasheet, P60D144PA4/9A24AFJ pinout, P60D144PA4/9A24AFJ application, or P60D144PA4/9A24AFJ equivalent, key selection criteria include dual-interface concurrency, Common Criteria–certified security architecture, 25-year EEPROM data retention, AIS-31–compliant TRNG, and support for MIFARE Plus/DESFire EV1 optional firmware.
Technical Context
The P60D144PA4/9A24AFJ implements a modular SmartMX2 architecture with orthogonal 8-/16-/24-/32-bit CPU instructions optimized for low-power secured smart card execution. Its Fame2 coprocessor delivers accelerated RSA/ECC operations, while the SBC interface supports parallel AES and Triple-DES key/data register loading.
Hardware security includes active/dynamic shielding, multi-sensor fault detection (voltage, temperature, clock, light), electronic fuses, and memory protection via MMU with System/User mode separation. The device enables true concurrent contact and contactless communication without resource contention, backed by CRC-16/32 coprocessors and watchdog timer for secure code execution.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| EEPROM | 144 KB user space; 25-year data retention, 500k write cycles, byte-to-256B programmable granularity |
| ROM | 384 KB; contains certified crypto library and secure boot firmware |
| RAM | 8.125 KB total: 5.5 KB CXRAM (CPU-accessible), 2.625 KB FXRAM (Fame2/CPU shared) |
| Crypto Acceleration | Fame2 coprocessor for RSA/ECC; SBC interface supporting AES-128/192/256 and Triple-DES in hardware |
| Interfaces | ISO/IEC 7816 UART (T=0/T=1); ISO/IEC 14443A CIU (106–848 kbit/s); fully concurrent operation |
| Supply Voltage | 1.62 V to 5.5 V continuous operation; supports Class A (5 V), B (3 V), C (1.8 V) modes |
| Security Certification | Common Criteria EAL5+ certified; AIS-31–compliant TRNG; integrated light/voltage/temperature/frequency sensors |
Pinout & Package
Package: MOB4 - contactless chip card module (super 35 mm tape format, 320 μm thickness, SOT500-2).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD | Power supply input | Accepts 1.62–5.5 V; powers all digital and analog blocks including RF front-end |
| VSS | Ground reference | Primary return path for digital logic, analog circuits, and RF interface |
| RST_N | Active-low reset input | Asynchronous hardware reset; initiates secure boot sequence and memory initialization |
| CLK | External clock input | Supports external crystal or oscillator; feeds clock generation and filtering circuitry |
| IO1–IO3 | Programmable I/O pins | Configurable as general-purpose I/O or dedicated functions (e.g., debug, test, auxiliary control) |
| LA/LB | RF antenna interface | Differential RF port for ISO/IEC 14443A contactless communication; matched for small-antenna designs |
Key Features
| Feature | Design Value |
|---|---|
| Concurrent dual-interface operation | Simultaneous ISO/IEC 7816 and ISO/IEC 14443A transactions without arbitration delay or CPU overhead |
| Memory Management Unit (MMU) | 16-segment cache with System/User mode isolation enabling secure multi-application OS execution |
| Copy Machines | DMA engines transferring data between SFRs, RAM, and EEPROM without CPU intervention-reducing latency and attack surface |
| Hardware TRNG | AIS-31–certified entropy source feeding cryptographic key generation and session randomness |
| Optional MIFARE Plus/DESFire EV1 | Firmware-implemented functionality enabling application convergence on single platform without hardware change |
Applications
| E-Passports | ID Cards |
|---|---|
Use Scenario: Biometric data storage and PKI-based authentication during border control verification. IC Role / Device Role / Timing Role: Secure host controller managing ECC signature generation, AES-encrypted biometric template storage, and contactless T=CL protocol stack. Use Value: Enables concurrent contact (e.g., officer terminal) and contactless (e.g., reader gate) access to protected EFs with hardware-accelerated crypto and tamper-resistant execution. | Use Scenario: National identity issuance with multi-application support (health, voting, tax). IC Role / Device Role / Timing Role: Dual-interface smart card controller executing certified JavaCard OS, enforcing memory partitioning via MMU, and managing secure applets. Use Value: Delivers 144 KB EEPROM capacity for multiple applets plus 25-year data retention-critical for long-lifecycle government ID programs. |
| Health Cards | Contactless Banking |
Use Scenario: Encrypted storage of patient records and insurance entitlements accessible via clinic terminals. IC Role / Device Role / Timing Role: Secure data vault with AES-256 encryption, TRNG-derived keys, and hardware-enforced read/write protection zones (32 B WOP, 14 B WP). Use Value: Meets HIPAA/GDPR requirements through physical memory protection, sensor-monitored execution, and certified crypto library. | Use Scenario: Tap-to-pay transaction with dynamic CVV and offline EMV approval. IC Role / Device Role / Timing Role: Contactless payment controller performing real-time DES/AES encryption, MAC calculation, and secure session key derivation. Use Value: Achieves sub-300 ms transaction time using Fame2 and SBC coprocessors-meeting EMVCo Level 1 timing requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar secure dual-interface smart card controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| P60D144PX1 | Dual-interface module (8-contact PDM1.1 package); includes ISO/IEC 7816 contact pads + ISO/IEC 14443A RF interface | Requires physical card contact interface; suited for hybrid bank cards with magstripe/chip/contactless | Select P60D144PX1 when contact interface is mandatory; P60D144PA4/9A24AFJ is contactless-only MOB4 form factor |
| J3A081M016 | Infineon SLE 78 family; 128 KB EEPROM, 32-bit CISC CPU, DES/AES/RSA acceleration, Common Criteria EAL5+ | Same security level but different instruction set, toolchain (TriCore vs. SmartMX2), and memory mapping | Choose J3A081M016 only if migrating from existing Infineon-based infrastructure; not pin-compatible or firmware-compatible |
Compared with P60D144PX1, P60D144PA4/9A24AFJ eliminates contact pads for thinner contactless modules, while versus J3A081M016 it offers superior concurrent dual-interface throughput and NXP's certified MIFARE/DESFire firmware stack-critical for transit and identity ecosystems.
Availability
P60D144PA4/9A24AFJ is available at Aetrix Electronics and suitable for e-passport personalization, national ID card production, and contactless banking card manufacturing requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for P60D144PA4/9A24AFJ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and identification markets.
The SmartMX2 P60 family-including P60D144PA4/9A24AFJ-is designed for high-security dual-interface smart cards, delivering Common Criteria–certified performance, RF excellence, and application convergence support for government ID, finance, and transit systems.
FAQ
What security certifications apply to the P60D144PA4/9A24AFJ?
The P60D144PA4/9A24AFJ is Common Criteria EAL5+ certified and implements AIS-31–compliant True Random Number Generation. Its security architecture includes active/dynamic shielding, multi-sensor fault detection (voltage, temperature, clock, light), electronic fuses, and memory protection via MMU with System/User mode separation-all verified per the SmartMX2 platform certification. These features are integral to the P60D144PA4/9A24AFJ silicon design and documented in NXP's official CC certification reports.
Does the P60D144PA4/9A24AFJ support both contact and contactless interfaces simultaneously?
Yes, the P60D144PA4/9A24AFJ supports fully concurrent ISO/IEC 7816 (T=0/T=1) and ISO/IEC 14443A (106–848 kbit/s) operation without resource contention. This is enabled by dedicated hardware blocks-including separate UART and CIU controllers-and Copy Machine DMA engines that offload data movement from the CPU. The P60D144PA4/9A24AFJ achieves true parallelism, allowing simultaneous contact-based personalization and contactless transaction processing.
What is the usable EEPROM capacity of the P60D144PA4/9A24AFJ for customer applications?
The P60D144PA4/9A24AFJ provides 146,944 bytes of usable EEPROM for customer OS and applications, excluding reserved areas for MIFARE Plus and DESFire EV1 implementations. This figure includes 78 bytes within protected security areas (14 B write-protected, 32 B write-once, 32 B read-only). Data retention is guaranteed for 25 years with 500,000 write cycles-verified per JEDEC JESD22-A117 standard and specified in the P60D144PA4/9A24AFJ datasheet.
Can the P60D144PA4/9A24AFJ execute MIFARE Plus or DESFire EV1 firmware?
Yes, the P60D144PA4/9A24AFJ supports optional implementation of MIFARE Plus and MIFARE DESFire EV1 functionality via firmware loaded into its EEPROM. This capability is explicitly confirmed in the SmartMX2 P60 family documentation and enables application convergence-allowing a single P60D144PA4/9A24AFJ platform to serve transit, access control, and loyalty use cases without hardware modification.
What package type is used for the P60D144PA4/9A24AFJ?
The P60D144PA4/9A24AFJ is supplied in MOB4 package: a contactless chip card module in super 35 mm tape format with 320 μm thickness and SOT500-2 footprint. This package omits contact pads and is optimized for thin, flexible contactless cards-distinct from dual-interface variants like P60D144PX1 (PDM1.1, 8-contact). The MOB4 form factor is defined in NXP's official ordering information table for P60D144PA4/9A24AFJ.
P60D144PA4/9A24AFJ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- -
- Series:
- *
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- -
- Core Size:
- -
- Speed:
- -
- Connectivity:
- -
- Peripherals:
- -
- Number of I/O:
- -
- Program Memory Size:
- -
- Program Memory Type:
- -
- EEPROM Size:
- -
- RAM Size:
- -
- Voltage - Supply (Vcc/Vdd):
- -
- Data Converters:
- -
- Oscillator Type:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
P60D144PA4/9A24AFJ FAQ
1.How can I place an order for P60D144PA4/9A24AFJ through Aetrix?
Please submit a Request for Quotation (RFQ) for P60D144PA4/9A24AFJ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for P60D144PA4/9A24AFJ reliable?
The price and inventory of P60D144PA4/9A24AFJ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for P60D144PA4/9A24AFJ is usually 5 days.
3.What payment methods are accepted for P60D144PA4/9A24AFJ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for P60D144PA4/9A24AFJ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for P60D144PA4/9A24AFJ?
P60D144PA4/9A24AFJ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your P60D144PA4/9A24AFJ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for P60D144PA4/9A24AFJ?
For technical support, including P60D144PA4/9A24AFJ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your P60D144PA4/9A24AFJ requirements.
6.How does Aetrix verify that P60D144PA4/9A24AFJ is sourced from the original manufacturer or authorized distributors?
All P60D144PA4/9A24AFJ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that P60D144PA4/9A24AFJ meets industry standards.
7.What is the process for return or replacement of P60D144PA4/9A24AFJ?
All P60D144PA4/9A24AFJ units undergo pre-shipment inspection (PSI). If there is an issue with P60D144PA4/9A24AFJ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The P60D144PA4/9A24AFJ part is unused and in its original packaging.
Return procedure for P60D144PA4/9A24AFJ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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